3 Replies Latest reply on Nov 26, 2018 4:20 PM by NileshB_06

    What is the length matching requirements for the Address, Data and control group of Async SRAM

    user_2283911

      Hello,

      We are using Async SRAM "CY7C1021DV33-10ZSXI" from cypress.

      As per datasheet and other design guideline document from cypress, there is no length matching requirements listed.

      but as it is a parallel bus, we believe there should be length matching requirements for these Address and control group and data group.

      so, let us know the length matching requirements for the Async SRAMs.

       

       

      Thanks and Regards

      Tarang Jindal