4 Replies Latest reply on Nov 11, 2018 9:42 PM by HirotakaT_91

    About designing with CY7C65634-48AXCT

    NoAr_1540581

      Q1) Please tell me the unused pin processing below?
      · Test I2C_SCL -> open?
      · OVR # [1] - [4] -> open?

      · PWR # I2C_SDA -> open?


      Q2) Is the recommended pull-up/pull-down value of SELFPWR, GANG pin 10 kΩ correct?

      Q3) The would like to know about the state of each terminal during reset, couldyou please share the list?

      Q4) Please tell me the internal equivalent circuit of the RESET#pin (in addition, it is included the protective diodes)

      Q5) Please tell me the internal equivalent circuit of the "open draininput pin" in datasheet page19?

       

       

      Best Regards

      Arai

        • 1. Re: About designing with CY7C65634-48AXCT
          HirotakaT_91

          A1)

          These are able to open since  Pad internal Pull Down Resistor or  Pad internal Pull Up Resistor is inside.

           

          A2)

          Pull-down resistor of greater than 100K is needed for Individual mode and a pull-up resistor greater  than  100K  is  needed  for  Gang  mode.

          Please refer to HX2VL datasheet.

           

          A3)

          I am sorry, but what do you mean? Would you like to know the detailed reset sequence? Please clarify.

           

          A4, A5)

          Basically, we do not offer internal circuit.

           

          NOTE: Kindly do not post a lot of question in one thread.

           

          Best regards,

          Hirotaka Takayama

          • 2. Re: About designing with CY7C65634-48AXCT
            HirotakaT_91

            A3)

            We do not have such a list, so far.

            Why the end customer needs these information?

             

            The power on reset can be triggered by external reset or internal circuitry. The internal reset is initiated, when there is an unstable power event for silicon’s internal core power(3.3V).

            The internal reset is released after approximately 2.7 micro-seconds of stable internal core voltage. The external reset pin continuously senses the voltage level (5V) on the upstream VBUS. In the event of USB plug/unplug or drop in voltage, the external reset is triggered.

             

            After releasing a reset, chip will be initial state.

             

            Best regards,

            Hirotaka Takayama

            • 3. Re: About designing with CY7C65634-48AXCT
              NoAr_1540581

              Takayama san

               

              A3)

              It is because their plan to connect PWR # etc to external circuit, so they want to check if there is something unstable during resetting. Is it possible to explain about the state of each terminal( other than reset pin)  during reset even though Cypress does not have such a list.

               

              Best Regards

              Arai

              • 4. Re: About designing with CY7C65634-48AXCT
                HirotakaT_91

                Which reset are you talking about? Power ON Reset or external reset?

                As a premise, power on reset is used for stabling pins.

                Do not use pins before being released. Because pins are unstable.

                 

                After Power ON Reset, RDN or RUP Type pins are set to Low or High.

                Other pins settings would be depended on customer circuit.

                 

                Please let me know which pins or flow you are concerned?

                Best regards,

                Hirotaka Takayama