5 Replies Latest reply on Dec 2, 2018 9:54 PM by KandlaguntaR_36

    FPGA(zc702) cannot receive data from fx3 in stream out mode



      In our system, the CYUSB3KIT-003(synchronous slave fifo 2 bit mode) and xilinx zc702 are used.

      in stream_in mode(streamin.img), the system worked normally; but in stream_out(streamout.img) mode, FPGA cannot receive the data from FX3 (please see attachted files)

      the control signals from fpga : SLCS is low, SLWR is high, SLOE is low, SLRD is low, FLAGC turns low, PKEND is high, A[1:0]=2'b11

      but there is no validate data on the data bus ~

      why can this happen and how to figure this out?

      Thanks so much~