Please attach your PSoC Creator project here for us to debug.
This is quite a large project implementing Cypress’ Power Line Communication system ( AN76458)) (did you see my article on the PLC in in Circuit Cellar Oct 2018 issue?). I believe that the rest of the circuitry will confuse the issue and anyway I am reluctant to put proprietary software out in the community/public domain. I have not got the time at the moment to produce a simplified version.
I was investigating the different addressing models to use on this project with an eye to using the information to publish a new blog/article on the subject. I have already written about adding a 9th bit on PC communications (EDN design idea) as well as Cypress AN2269 on adding the 9th bit to UART communications on the PSOC1. SO it would seem logical to continue the theme.
However I have become disillusioned with the idea for a number of reasons, one of which being the discontinuation of Cypress support in favour of this forum. Since I have got the Software Byte by Byte working, I have shelved the concept.
Add code to RX ISR which will be detect the address byte(check UART_RX_STS_MRKSPC status), and move the correctly addressed data bytes to the buffer(along with address byte). Read from FIFO but skip all not addressed data.
Please ensure you are using latest version of PSoC Creator i.e. PSoC Creator 4.2 .
Please check the above two and let us know whether they are working.
Thanks and regards