8 Replies Latest reply on Nov 9, 2018 12:02 AM by marcin_3377571

    problem with quick power off/on CYW43907

    marcin_3377571

      Hello,
      I have a problem with chip - CYW43907. When I switch power off/on (power supply) quickly (less then 1s) chip is hanging - it is not showing data on console. The state of chip is undefined and I can wait forever - state is not changing. To make it working again I need to power off/on again (and this time wait more than 1s). Have you seen such behaviour?

      Is it possible that it is connected with internal POR treshold? To what voltage RESET line should get to properly reset the chip? Can I change reset voltage treshold?

       

      Best,

      Marcin

        • 1. Re: problem with quick power off/on CYW43907
          zhez

          Hello:

             I guess you are going with a lower wiced version,  I update to 6.2.1.2 this issue is gone.

          1 of 1 people found this helpful
          • 2. Re: problem with quick power off/on CYW43907
            marcin_3377571

            Hello,

            thank you for your help. After your suggestion  I upgrade my SDK to 6.2.1.2 and unfortunately in my case it did not help. I would be very grateful if someone will help me to understand:

            - what voltage RESET line should get to properly reset the chip, can we control it?

            - how POR is working on this chip and is it possible to control it?

             

            I will be grateful for any other ideas,

            Marcin

            • 3. Re: problem with quick power off/on CYW43907
              zhez

              Hi:

                  can't find any info we can control the internal POR circuit, here is the timing instruction from the spec:

              I misunderstood the question,   now I try to test the power off/on quickly in my evb, it is hard to duplicate the issue.    Are you using your own designed board for the test ?

               

              Note: The CYW43907 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after
              VDDC and VDDIO have both passed the POR threshold.
              Note: The 10%–90% VBAT rise time should not be faster than 40 microseconds. VBAT should be up before or at the same time as
              VDDIO. VDDIO should not be present first or be held high before VBAT is high.

              • 4. Re: problem with quick power off/on CYW43907
                marcinwilk

                Hello,

                I have problem on my own PCB. I checked after your suggestion on EVB and there is no issue.. So it  must be connected to my hardware design. I checked on Logic Analyzer - reset line, VDDIO and VBAT. Voltage is quicly dropping only to 0,4V - I think that this might be an issue. Maybe reset line should go below 0.4V before going up again? Do you know maybe what is the voltage treshold to correctly reset chip? Maybe someone has schematic with typical CYW43907 application to share with me - it could help me to spot potential error in our HW design? Thanks for any help.

                 

                Best,

                Marcin

                 

                reset_line.png

                • 5. Re: problem with quick power off/on CYW43907
                  zhez

                  Hello:

                  just add my comments here:

                  1. need to check vbat and vddio timing:

                  The 10%–90% VBAT rise time should not be faster than 40 microseconds. VBAT should be up before or at the same time as

                  VDDIO. VDDIO should not be present first or be held high before VBAT is high.

                   

                  2.  have a check on bootstrap to see if there has any difference with reference.

                  3.  check the reset circuit,   we have description in the starting guide:

                   

                  The CYW43907 device can be reset using the “Target Reset” switch SW2 or a reset command from the onboard programmer/debugger and serial interface chip, as shown in Figure 4-3. The CYW43907/BCM43907 datasheet states that HIB_REG_ON_IN needs to be delayed by at least 2 cycles of the 32.768-kHz clock after VBAT and VDDIO have reached 90% of their final values. To ensure proper boot-up, the RC delay circuit for HIB_REG_ON_IN is essential as shown in Figure 4-4.

                  1 of 1 people found this helpful
                  • 6. Re: problem with quick power off/on CYW43907
                    marcin_3377571

                    Hello,

                    I could not be more happy to say that your solution to add RC circuit on HIB_REG_ON_IN line worked!

                     

                    Thank you for your advises and help.

                    One last question is: Did you know where I can find datasheet with Figure 4-4? As one I have do not have this figure and I just added RC circuit with values I thought will be ok.

                     

                    Or maybe you can share what values are recommended to RC delay circuit?

                     

                     

                    Regards,

                    Marcin

                    • 7. Re: problem with quick power off/on CYW43907
                      zhez

                      Hi :

                       

                      here is the RC circuit.

                      • 8. Re: problem with quick power off/on CYW43907
                        marcin_3377571

                        Thank you very much!