1 Reply Latest reply on Nov 7, 2018 11:03 PM by BragadeeshV_41

    Changing SPI pins on the fly



      We have the need of reconfiguring a (SCB) SPI Master while the system is running. We need to re-assign it to different pins (MOSI, MISO, CLK, SS). Of course the specific SPI block doesn't have to be active when it's being reconfigured, but the rest of the system should.


      To achieve this we should have to reconfigure the port configuration (GPIO_PRTx_* registers) as well as the DSI (UDB_DSI_* registers). However, it's hard to find documentation for the DSI interconnect and its registers. Is there a logical "map" of this part of the PSoC available? The "Top Level Architecture" figure in start of section D of the TRM doesn't give any details. Compare this with the excellent documentation of the UDBs (for instance figure 32-4 "PLD Macrocell Architecture").


      Creating the two different configurations and checking the differences in the generated cyfitter_cfg.c gives some information, but the diff is probably bigger than it has to be - the compiler may very well change other, unrelated things, due to such a change.


      We want to be able to switch to use pins 0, 1, 2, 4 from port 9 or port 3.


      Thanks, Jacob