First of all, you can refer to the component's datasheet from its configure Dialog.
Meantime, although written for PSoC4, following 2 application notes seem to be very helpful information.
(I've tried polling and dma samples and they worked fine.)
CE224339 - PSoC 4 SPI Master
CE224463 - PSoC 4 SPI Slave
1. Recently I encountered similar question.
The SPIS writes 0 in the first byte of the buffer.
So if we want to send 7 bytes, let's say data~data.
We need to first call SPIS_WriteTXDataZero() with data.
Then we need to SPIS_WriteTxData for data, ... data.
Note: Please refer to the datasheet of SPIS
So I would try
With the application notes mentioned above,
I did not notice that we need extra cycle for the master to
clock out the last data, but as far as I tried today,
yes, I needed the "one more" byte cycle.
2. According to the datasheet of SPIM, FIFO is implemented
using 4-byte/word FIFO, and I suppose this is causing interval(s)
between each 4bytes.
3. As you showed in 2. the transaction(s) took place in 2 parts,
and I suppose the ISR was called at the first transaction.
As far as I tried with CY8CKIT-046, ISR was called multiple times
Attached is my trial with CY8CKIT-046 based on your project.
Hopefully the "main.c" will work for PSoC 5...
Hello, thank you responding to my message. Do you know if actual SPI Slave Devices that have SPI Mode CPHA(0),CPOL(0) require an extra byte from the Master? Or, is that just present with PSoC SPI modules? I'm using the PSoC5 to interface with a XRA1403 GPIO expander. The dataheet does not mention this extra byte, so I'm contacting the company.
Last, when I send the extra byte I get all 8 words in Slave receiver buffer in the ISR.
Another thing, I changed the Interrupt "Interrupt Type" to Level. After making this switch the I was able to read all 8-bytes in the Slave Receive buffer. Perhaps I will missing an interrupt before and this change fixed things.
With your reply, I played with my code a little more and
I added a debug line to display remaining slave's rx buffer size,
and I noticed that there was 1 buffer left unread.
Then I added some lines to salvage remaining rx buffer of Slave to the dsp_spi_rcv_buffer.
After this without sending one more byte cycle my program can receive all 7 bytes.
So my conclusion is it was matter of interrupt timing and using SPIS_WriteTxDataZero()
does not add requirement of additional byte clock.
Attached is my updated project for CY8CKIT-046 and I "hope" that the main.c should be usable for 5LP, too.
I have written at least several programs using SPI slave device(s) with MCUs including Cypress, NXP,
and I have never seen a slave device which requires an extra byte for sending data.
And as I wrote in my previous reply, PSoC's SPIS also does not require an extra byte,
at least it was receiving the data into its rx buffer.
So I don't think you need to worry about the extra byte sending with XRA1403.