If I program this oscillator to have LVDS output waveform logic at supply voltage Vdd = 1.8V, it's evident through a few of your application notes and testing that this combination does not exhibit standard output waveform voltage values for LVDS logic (voltage is too low).
In the above app note, it says the LVDS 1.8V combination requires the output common mode voltage (VOCM) to be supplied externally (along with implementing AC coupling between the clock device and the receiver circuit) in order to exhibit standard output waveform voltage values -
Question:
Is there a certain value Cypress suggests to apply for the external output common mode voltage?