As said in the page #27 (#6) of AN87216, it is expected that there would be zeros (0) on the received side, if you send the data size is not mutliple of 4 bytes. Because the data bus width is 32-bit (4 byte).
In first case, you have sent 14 bytes, it is expected to receive 16 bytes (with 2 last two bytes as zeros). But in you case you have received 20 bytes.
If you check the patten, the last 4 bytes (17,18,19,20 bytes) are same as 13,14,15,16 bytes. This may be due the sampling of bus twice.
Can you please probe the PKTEND, SLWR and SLCS, data bus and share the timing diagrams?
Please send data size multiple of 4 bytes and check whether there is repition of last 4 bytes. Share the screen shot with us.
Hi Anil Srinivas,
Please find the timing diagram capturing 16 bytes data (0x30, 0x31, 0x32...0x64, 0x65, 0x66) (0-f) transmitted by master. Are the last 4 bytes received by slave end packet bytes?
Also, please refer to "Not write data in SHORT_PKT.jpg", I have removed "IN_DATA" by unchecking "sample data from data bus" and "write data into data sink", number of data received by master is correct. And zero length data is received too after clicking transfer Data-IN again.
Then I tested the BULK IN of slave by sending out 8 k bytes data (8192_Count.hex) from master. it seemed that slave can only receive (512 bytes * 8 times) and was unable to send or receive data anymore.
The error message shown in control center was as below.BULK IN transfer
BULK IN transfer failed with Error Code:997
Which source files I have modified are shown as below:
In cyfxslfifosync.h,#define CY_FX_SLFIFO_DMA_BUF_COUNT (16) /* Slave FIFO channel buffer count */
#define CY_FX_SLFIFO_DMA_TX_SIZE (0) /* DMA transfer size is set to infinite */
#define CY_FX_SLFIFO_DMA_RX_SIZE (0) /* DMA transfer size is set to infinite */
#define CY_FX_SLFIFO_THREAD_STACK (0x0400) /* Slave FIFO application thread stack size */
#define CY_FX_SLFIFO_THREAD_PRIORITY (8) /* Slave FIFO application thread priority */
#define CY_FX_EP_PRODUCER 0x01 /* EP 1 OUT */
#define CY_FX_EP_CONSUMER 0x81 /* EP 1 IN */
#define CY_FX_PRODUCER_USB_SOCKET CY_U3P_UIB_SOCKET_PROD_1 /* USB Socket 1 is producer */
#define CY_FX_CONSUMER_USB_SOCKET CY_U3P_UIB_SOCKET_CONS_1 /* USB Socket 1 is consumer */
/* Used with FX3 Silicon. */
#define CY_FX_PRODUCER_PPORT_SOCKET CY_U3P_PIB_SOCKET_0 /* P-port Socket 0 is producer */
#define CY_FX_CONSUMER_PPORT_SOCKET CY_U3P_PIB_SOCKET_1 /* P-port Socket 1 is consumer */
In cyfxslfifosync,CyU3PGpifSocketConfigure(0, CY_U3P_PIB_SOCKET_0, 4, CyFalse, 7);
CyU3PGpifSocketConfigure(1, CY_U3P_PIB_SOCKET_1, 0, CyFalse, 1);
Is the DMA buffer overflow? Please kindly advise. Thanks.
For more information, I added "CyU3PDebugPrint(6, "\r\nJackie, P to U count =%d\n", input->buffer_p.count)" in CyFxSlFifoPtoUDmaCallback as below:
void CyFxSlFifoPtoUDmaCallback (
CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
if (type == CY_U3P_DMA_CB_PROD_EVENT)
/* This is a produce event notification to the CPU. This notification is
* received upon reception of every buffer. The buffer will not be sent
* out unless it is explicitly committed. The call shall fail if there
* is a bus reset / usb disconnect or if there is any application error. */
status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0);
CyU3PDebugPrint (6, "\r\nJackie, P to U count =%d\n", input->buffer_p.count);
if (status != CY_U3P_SUCCESS)
CyU3PDebugPrint (4, "CyU3PDmaChannelCommitBuffer failed, Error code = %d\n", status);
/* Increment the counter. */
Then the program stucks.
I reported the program stuck when FX3 board with “auto Master” firmware transmitted 8K bytes data to FX3 board with “Slave FIFO sync” firmware. In this case, USB 2.0 ports of PC were used. But when I changed to use USB 3.0 ports, the program of slave side didn’t stuck although only 6144 bytes were received by slave. Thanks.
-Please share above similar debugging prints of master.
Hi Anil Srinivas,
Master (AutoMaster.img, prebuilt image of AN8721) is run in AUTO DMA, how to print the data count?
Can you duplicate my problem? Do you have any idea to fix it? Thanks.
Please refer to Application note "AN87216", The chapter 9 of document explains Transfer data to the Bulk OUT endpoint of slave FX3 and read back the same data from Bulk in the endpoint of master FX3 in deatail, Please follow the same steps.
I have already read "AN87216". I know the slave FIFO sync uses MANUAL DMA that is different from auto slave using AUTO DMA. I don't know why the slave stucks when receiving a large packet of data. Hope you can help me to solve the problem.