1 Reply Latest reply on Oct 30, 2018 10:46 PM by psyu

    External crystal drive level calculation

    bruce

      I am working on a new board design using the PSoC 5LP and I would like to get some more information on how to calculate / predict the crystal drive strength of the PSoC 5LP MHz External Crystal Oscillator subsystem, more specifically the 4 – 25 MHz ECO.

       

      I’ve read through AN54439 “PSoC 3 and PSoC 5LP External Crystal Oscillators” and consulted the PSoC 5LP TRM but I can’t seem to find the specification / calculation of crystal drive strength.  Section 6.1.2 of AN54439 does provide an equation to calculate drive level based on a measurement of RMS current: DL = I(rms)^2 * ESR -- however, this provides no information on how to calculate/predict the I(rms) current flowing through the crystal during the design phase of a project.   I understand it can be measured after boards are assembled and PSOC programming is complete, but that is not much help when it comes to up-front part selection and picking a crystal of sufficient power rating.

       

      Table 2 in section 7 of AN54439 provides some data of “Max Expected Drive level” for various crystals and frequencies, but these seem to be simply measured results rather than calculations or predictions. Is there any way to predict the drive level based on the crystal frequency / load capacitance / ESR and the corresponding setting of the Amplifier Gain (AMPIADJ) register? 

       

      Reading through the TRM documentation it seems like the relevant registers are:

      • - FASTCLK_XMHZ_CFG0: xcfg field
      • - FASTCLK_XMHZ_CFG1: vref_sel_wd and vref_sel_fb fields

       

      In my specific application I would like to use a 24MHz crystal.  I am able to select a load capacitance of >15pF or <15pF, so according to the TRM I should be setting FASTCLK_XMHZ_CFG0:xcfg to either 5’h19 or 5’h13 (C0 is typically >3.5pF for the crystals I’ve been looking at so 5’h17 is likely not the best value).

       

      Similarly, according to the TRM I should be setting FASTCLK_XMHZ_CFG1: vref_sel_wd to 3’h3 and vref_sel_fb to something >= 4’h3 (for minimum drive I should set to 4’h3).   What I would like to know is if I set the registers this way, what will be the resulting drive level?

       

      I’ve found calculations from other manufacturers that claim to calculate drive level based on drive voltage, frequency, capacitance, and ESR.  For example:

      cypress1.jpg

      (where VDD is the peak voltage)

      Or

      cypress2.jpg

      (where Vpp is the peak-to-peak voltage)

       

      These two calculations from two different sources are equivalent, but when I apply those equations to the specific crystals listed in AN54439 section 7 and use the drive voltages given in the TRM description of the FASTCLK_XMHZ_CFG1 register I get very different results from the values provided in Table 2.  The calculated results are much lower than the results presented in AN54439.

       

      cypress3.jpg

       

      For example if I plug in the crystal information from ECS for the first crystal in the list, and use a feedback value of 0x3 (=277mV according to the TRM) I get a much lower drive level.  If I interpret the 277mV as the peak voltage, I calculate 17uW.  If I interpret it as peak-to-peak I calculate 4.3uW.  If I interpret it as RMS I get 34uW.

       

      Looking at the content of the table, I also don’t understand a couple of other things:

      1. In the second row, why is the AMPIADJ parameter for the crystal ECS-240-12-5PX-TR set to 0x17.   According to Table 1 in the same AN54439 app note, a setting of 0x17 is only for crystals with a C0 spec of < 3.5pF, but that particular crystal has a C0 of 7pF, the exact same as the ECS crystals above and below it in the table.  Shouldn’t the AMPIADJ setting be 0x13?
      2. Why does that same crystal have such a high drive level?   It is exactly the same as the one below it in the table, other than having a lower load capacitance.   Every equation I have seen shows that drive level should be decreased with a lower load capacitance, not increased, so why is the drive level so high?

       

       

      How am I able to predict the drive level so I can specify the correct crystal?   Am I misinterpreting the feedback value in the table and/or in the TRM?  Are the equations above incorrect in some way?  Or is there some other PSOC setting I’m not accounting for?

       

      The safest approach would seem to be to specify a large crystal package capable of 500uW.  However due to board size constraints I would much rather specify a small surface mount crystal that is only rated to 100uW or 200uW.   If I trust the design calculations of other manufacturers and use the minimum setting for FASTCLK_XMHZ_CFG1 (assuming the voltage levels in Table 1-43 of the TRM are correct) I would expect to be well below 100uW if I choose the rest of the crystal specs carefully – however given the high drive levels listed in Table 2 of AN54439 and my inability to recalculate those measured values I can’t be sure.

       

      Thanks in advance,

      Bruce