CX3: receiving max speed (2.4Gbps) bursts

Hi,

with my CX3-based board and my FW I'm currently able to receive bursts (lines, or HS packets) at 2.4Gbps, which is the maximum nominally supported by the 24-bits 100 MHz max parallel interface, but only as long as the burst size (HS packet payload) is less than around 9 kB.

This makes some sense because so far I've not been able to use the maximum clock speed on the parallel interface, as I'm stuck with the following somehow working configuration, that results in a parallel bus clock of 96 MHz:

CyU3PMipicsiCfg_t cfg;

cfg.dataFormat = CY_U3P_CSI_DF_RGB888;

cfg.numDataLanes = 4;

cfg.pllPrd = 2;

cfg.pllFbd = 119;

cfg.pllFrs = CY_U3P_CSI_PLL_FRS_250_500M;

cfg.csiRxClkDiv = CY_U3P_CSI_PLL_CLK_DIV_4;

cfg.parClkDiv = CY_U3P_CSI_PLL_CLK_DIV_4;

cfg.mClkCtl = 0;

cfg.mClkRefDiv = CY_U3P_CSI_PLL_CLK_DIV_2;

cfg.hResolution = 0;

cfg.fifoDelay = 0;

CyU3PMipicsiSetIntfParams(&cfg, CyFalse);

In my understanding in this configuration the FIFO slowly fills up (as it is filled at 100 MHz and emptied at 96 MHz) and it overflows when the burst/line/packet payload is too big. Please note that I did not find, experimentally, any influence of the hResolution (BYTE_COUNT) parameter: any value there leads to a working case.

On the other hand I verified experimentally that the fifoDelay parameter has the expected effect: I need to use low values to keep the configuration working, otherwise I observe silently corrupted captured data, the same problem that I see when I increase the payload size.

So I have a qualitative explanation for this somehow working configuration, even if I'm still struggling with the quantitative part (but the size of this FIFO is not well described in the available documentation). I'm also not sure that there is no way of being notified of a FIFO underflow/overflow (rather than checking the captured data), but this is my understanding as of now.

This said, my current problem is that the following very similar configuration is not working at all:

CyU3PMipicsiCfg_t cfg;

cfg.dataFormat = CY_U3P_CSI_DF_RGB888;

cfg.numDataLanes = 4;

cfg.pllPrd = 2;

cfg.pllFbd = 120;

cfg.pllFrs = CY_U3P_CSI_PLL_FRS_250_500M;

cfg.csiRxClkDiv = CY_U3P_CSI_PLL_CLK_DIV_4;

cfg.parClkDiv = CY_U3P_CSI_PLL_CLK_DIV_4;

cfg.mClkCtl = 0;

cfg.mClkRefDiv = CY_U3P_CSI_PLL_CLK_DIV_2;

cfg.hResolution = 0;

cfg.fifoDelay = 0;

CyU3PMipicsiSetIntfParams(&cfg, CyFalse);

The only difference, in my understanding, is that I'm trying to use a 96.8 MHz clock rather than a 96 MHz one, so that the FIFO should still be slowly filling up, but slower than in the working configuration. I would expect this slower filling rate to increase the maximum payload size.

Unfortunately in this second configuration I'm not able to receive a single byte: nothing happens and a time-out gets triggered at application level (PC-side) without anything being signaled on the CX3 side (I don't have any watchdog there). The pllFbd value is the only difference in the entire application comparing the two configurations.

My sensor is clocked autonomously, so I'm not using MCLK.

Please note that my original goal was using pllFbd = 125, for obtaining the targeted 100 MHz clock, but in that case the behavior is identical to the 120 case described above; actually I landed on the 119 value by experimenting and on top of unexplained failures with higher values.

Any clue of what is happening here ?

Thank you and best regards, Nicola.