Being dedicate Opamp input pins, P1/P1 may have very small different Internal parasitic capacitance compare with other pins, but this won't have so big affection on sensor sensitivity, there should be other reason. Is other any external cap on P1/P1 or different series R value?
Hi, thanks for the info, so are there any other things that could cause
this, like the on-chip routing? Is there a way to see where/how it ended
up routing each pin?
Please confirm the external circuit on P1/P1 are the same as other sensors. Actually our PSOC4 DVK CY8CKIT-042 (based on CY8C4245AXI-483 ) also used P1 as an touch sensor pin, sensitivity have no no different with other sensors.
So yes, all the external circuits are identical, basically just wires
that go to a connector that go to a separate flex circuit with the
Our design has 23 electrodes, Is it possible that some of them had to be
internally routed through a less-ideal way? (Not sure how the PSoC 4
does its internal connections but I know on the PSoC 5, we've run into
this issue). Is there a way to see how it was routed?
I recommend you enable the BIST(build in self test) option in CSD component, read the Cps of each sensor out, then we can see if the sensor cp of P1/P1 is abnormal compare with others. About the analog routing, no customer report CapSense sensor routing have issue(you know we have lots of CapSense customers).
If possible, you can upload your project, we can check if there has issue.