8 bit GPIF II interface

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ThM_3776866
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Hi all,

is it possible to 8 bit GPIF II interface and how?

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1 Solution

Thrimuthi M,

The following information may help you.

Question: What are changes to be done in the firmware provided with AN65974 to build firmware for 8-bit and 24-bit Slavefifo applications?

Answer: The firmware provided with AN65974 works for 16-bit and 32-bit Slavefifo by modifying the macro defined in cyfxslfifosync.h file - CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to '0' and '1' respectively. This firmware doesn’t work for 8-bit and 24-bit Slavefifo applications.

Do the following to make the AN65974 project work for 8-bit bus width (or 24-bit bus width).

  1. Open the GPIF project provided with AN65974. Once the project is opened, the Interface Definition window is displayed as show in Figure 1
  2. Select 8 Bit in Data bus width in the left pane (select 24 Bit if 24-bit bus width is required) as shown in Figure 2.                                                                         Figure 1. Interface Definition Window of AN65974 GPIF Project

                                      pastedImage_8.png

                                                                 Figure 2. Selection of 8 Bit in the Data Bus Width

                               pastedImage_13.png

3. Save it and build the project by clicking Build > Build Project to generate the cyfxgpif2config.h file as shown in Figure 3.

                                                       Figure 3. Building the Project and Generating the New cyfxgpif2config.h File

                                pastedImage_14.png    

4. Save it and build the project by clicking Build > Build Project to generate the cyfxgpif2config.h file as shown in Figure 3.

5. Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to '0' in the cyfxslfifosync.h file.

6.Build the project. This step generates the image file for the 8-bit Slavefifo application (for 24-bit Slavefifo if 24 Bit is selected in step 3).

Note: When the data bus width is changed to 8-bit, the address lines are mapped to GPIO 8 (A1) and GPIO 9 (A0), unlike GPIO 28 (A1) and GPIO 29 (A0) in the case of both 16-bit and 32-bit bus widths. Similarly, with the 24-bit bus width, address lines are mapped with GPIO 41 (A1) and GPIO 42 (A0). Pin mapping for address lines may change based on the number of control lines, data bus width, and number of address lines selected. Ensure that the external processor drives the address lines that are mapped to the GPIF interface per the selected bus width, number of address lines, and number of control lines.

 

Figure 3. Building the Project and Generating the New cyfxgpif2config.h File

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7 Replies
SrinathS_16
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Hello,

FX3 GPIF II supports 8, 16, 24 or 32 bit data bus. Please refer to the AN75779 example for a reference of the 8-bit GPIF II.

Best regards,

Srinath S

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ThM_3776866
Level 4
Level 4
First like received First like given Welcome!

Thank you srinath sir

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ThM_3776866
Level 4
Level 4
First like received First like given Welcome!

Hai,

I have doubt in 8 bit GPIF interface source code. In the source code enabling the DQ32bit which meas 32 bit GPIF interface right?

how we can configure 8 bit GPIF interface or both the case DQ32 bit is true.

GPIF.PNG

Thank you.

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Hello,

To use the GPIF II interface in 8-bit data bus width mode, set the isDQ32bit as CyFalse and select the 'Data Bus Width' as '8 bit' in the GPIF II Designer tool.

pastedImage_0.png

Best regards,

Srinath S

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ThM_3776866
Level 4
Level 4
First like received First like given Welcome!

Hello,

Thanks for your replay,

I don't know about GPIF II Designer tool and use. Is any manual is there for GPIF ll tool.

Best regards,

Thrimurthi M

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Attachments are accessible only for community members.

Hello Thrimurthi M,

Please find the attached document. This is present as part of the FX3 SDK at the below path.

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\GPIFII_Designer

Best regards,

Srinath S

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Thrimuthi M,

The following information may help you.

Question: What are changes to be done in the firmware provided with AN65974 to build firmware for 8-bit and 24-bit Slavefifo applications?

Answer: The firmware provided with AN65974 works for 16-bit and 32-bit Slavefifo by modifying the macro defined in cyfxslfifosync.h file - CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to '0' and '1' respectively. This firmware doesn’t work for 8-bit and 24-bit Slavefifo applications.

Do the following to make the AN65974 project work for 8-bit bus width (or 24-bit bus width).

  1. Open the GPIF project provided with AN65974. Once the project is opened, the Interface Definition window is displayed as show in Figure 1
  2. Select 8 Bit in Data bus width in the left pane (select 24 Bit if 24-bit bus width is required) as shown in Figure 2.                                                                         Figure 1. Interface Definition Window of AN65974 GPIF Project

                                      pastedImage_8.png

                                                                 Figure 2. Selection of 8 Bit in the Data Bus Width

                               pastedImage_13.png

3. Save it and build the project by clicking Build > Build Project to generate the cyfxgpif2config.h file as shown in Figure 3.

                                                       Figure 3. Building the Project and Generating the New cyfxgpif2config.h File

                                pastedImage_14.png    

4. Save it and build the project by clicking Build > Build Project to generate the cyfxgpif2config.h file as shown in Figure 3.

5. Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to '0' in the cyfxslfifosync.h file.

6.Build the project. This step generates the image file for the 8-bit Slavefifo application (for 24-bit Slavefifo if 24 Bit is selected in step 3).

Note: When the data bus width is changed to 8-bit, the address lines are mapped to GPIO 8 (A1) and GPIO 9 (A0), unlike GPIO 28 (A1) and GPIO 29 (A0) in the case of both 16-bit and 32-bit bus widths. Similarly, with the 24-bit bus width, address lines are mapped with GPIO 41 (A1) and GPIO 42 (A0). Pin mapping for address lines may change based on the number of control lines, data bus width, and number of address lines selected. Ensure that the external processor drives the address lines that are mapped to the GPIF interface per the selected bus width, number of address lines, and number of control lines.

 

Figure 3. Building the Project and Generating the New cyfxgpif2config.h File