This is not a known issue with CYBLE-022001-00.
Can you reproduce this issue on CYBLE-022001-EVAL EZ-BLE™ PRoC™ Evaluation Board?
If yes, using a 'scope do you observe SCL being held low?
Please upload any relevant 'scope traces, hardware schematic PDF and PSoC Creator project for written for CYBLE-022001-EVAL board for everyone to have a look at it.
Thanks for your reply. Here are answers to your questions:
I am using the CYBLE-022001-EVAL board for development.
SCL is not being held low when using P5 for SCL signal. See picture
With no ACK being received, the I2C master issues a STOP and retry.
When SCL is assigned to P3 and SDA is assigned to P3, SCL clock
stretching and ACK occur:
I am attaching archive of two projects. One that uses I2C Slave and one
that uses EZI2C SCB configurations. Both function the same.
On Wed, Oct 24, 2018 at 2:01 PM Troy Gentry <email@example.com>
We tested your project with pin set to P5.0 and P5.1 and checked the output on an oscilloscope. Both the pins are working correctly as a digital output pin.