9 Replies Latest reply on Nov 28, 2018 1:02 AM by alamandaa_16

    SlaveFifoSync: Why flagb is always low?

    doch_3739346

      Hi,

       

      I've downloaded firmware reference design SlaveFifoSync, generated SF_shrt_ZLP.img.

      Made below changes to FPGA example slaveFIFO2b_fpga (VHDL version) code, generated bit file.

      1. Force mode to ZLP.

      2. Tied flagc and flagd to gnd.

      3. Add debug LED and probe signals.

       

      I can program firmware.

      2018-10-19 12_26_04-hhgw28_2 (dgc) - TightVNC Viewer.png

      Except one complete transfer, "Transfer Data-IN" always fail.

      2018-10-19 12_57_04-USB Control Center.png

      Noticed flagb is always low.

      2018-10-19 14_51_20-hw_ila_1.png

      Checked pin location constraint is matching with schematic.

       

       

       

      Why flagb is always low? How to fix this?

       

      Thanks!