8 Replies Latest reply on Oct 24, 2018 10:25 PM by SrinathS_16

    Altera FPGA + CY68013A Stream IN: data error

      Please see the attachment:

      1. Below is the hardware connections:

      2. Below is the CY68013 firmware:

      CY68013 configuration:

      1. 1) Internal 48MHz, output inverted 48M on the CLKOUT pin,  provide the clock to FPGA;
      2. 2) FLAGB – EP6FF, FLGA2 – EP2EF;
      3. 3) Internal 48MHz, Sync Slave FIFO interface;
      4. 4) EP2 & EP6 WORDWIDE=0, 8bit data width;

      3. Below is the FPGA Verilog:

           FPGA used CY68013’s CLKOUT to its work clock.

           When user press key down, drive “SLWR” to LOW;

       

      When SLWR = 0, FPGA send incremental data to CY68013.

      4. Below is the USB Data IN:

       

       

        • 1. Re: Altera FPGA + CY68013A Stream IN: data error
          SrinathS_16

          Hello,

           

          - Please check if the FIFOADR[1:0] pins are driven with the values corresponding to endpoint 6 (FIFOADR[1:0] = 10).

          - To identify the point of issue whether in the FX2LP or in the FPGA, turn off the FPGA and drive the SLWR, FIFOADR[1:0] pins and read data from the Control Center. The host application should read continuous FF.

           

          Best regards,

          Srinath S

          • 2. Re: Altera FPGA + CY68013A Stream IN: data error

            HI, Srinath:

                 As you said,

                 1) FPGA only output slwr=0, FIFOADR[1:0]= 0x2; no any data output, USB Console Center get contnuous FF, this is right.

               

                 Any other suggestions? thanks!

            • 3. Re: Altera FPGA + CY68013A Stream IN: data error

              HI, Srinath:

                  Could you help to check my CY68013 firmware from the attachment?

              CY68013 configuration:

                  1) Internal 48MHz, output inverted 48M on the CLKOUT pin,  provide the clock to FPGA;

                        -- the clock of CY68013 and FPGA are not synchronous?

                  2) EP2 & EP6 WORDWIDE=0, 8bit data width;

                         -- Maybe CY68013 work at 16bit data width?

              • 4. Re: Altera FPGA + CY68013A Stream IN: data error
                SrinathS_16

                Hello,

                 

                Can you please recheck if you have added the attachments? Also, attach the schematics corresponding to the FX2LP connections.

                 

                -- the clock of CY68013 and FPGA are not synchronous?

                - The FPGA receives its clock from the FX2LP for its operation. But, the interface between the FPGA and the FX2LP slave FIFO is over the IFCLK which is generated from the FX2LP internal clock. So, there should be no synchronization issues.

                 

                -- Maybe CY68013 work at 16bit data width?

                - FX2LP can work with both 8-bit and 16-bit data bus width. By default, the FX2LP is configured for 16-bit data bus width. To enable 8-bit data bus width, the EPxFIFOCFG register can be configured but in order to use the PORTD as normal GPIO, the WORDWIDE bit of all the FIFOs has to be cleared to 0.

                 

                Since, you have mentioned that the FX2LP receives FF's properly, the issue might most probably be with the FPGA code. Can you please recheck it once again?

                 

                Best regards,

                Srinath S

                • 5. Re: Altera FPGA + CY68013A Stream IN: data error

                  Hi, Srinath:

                       Thanks a lot!

                       Below is the hardware connections, can you help to review it?

                      

                  Best Regards!

                  Nathan.WU

                  • 6. Re: Altera FPGA + CY68013A Stream IN: data error
                    SrinathS_16

                    Hello Nathan.WU,

                     

                    The hardware schematics appear fine. In case you have referred the application note from Cypress, please try using the same FPGA code (if compatible with your hardware setup).

                     

                    Best regards,
                    Srinath S

                    • 7. Re: Altera FPGA + CY68013A Stream IN: data error

                      Hi, Srinath:

                           The attachment is my CY68013A firmware.

                       

                           Could you help to confirm whether the firmware confiurations are below? Thanks a lot!

                      1. 1) Internal 48MHz, output inverted 48M on the CLKOUT pin,  provide the clock to FPGA;
                      2. 2) FLAGB – EP6FF, FLGA2 – EP2EF;
                      3. 3) Internal 48MHz, Sync Slave FIFO interface;
                      4. 4) EP2 & EP6 WORDWIDE=0, 8bit data width;

                       

                      Best Regards!

                      Nathan.Wu

                      • 8. Re: Altera FPGA + CY68013A Stream IN: data error
                        SrinathS_16

                        Hello Nathan.WU,

                         

                        The firmware is fine. Please check if the modifications that you have performed to the FPGA code are suitable for 8-bit transfers.

                         

                        reg [7:0] data_out1;

                        ...

                        data_out1 <= 8'd0;

                         

                        Also, you can probe the data lines between the FPGA and FX2LP and check the data that is transferred on the interface.

                         

                        Best regards,

                        Srinath S