3 Replies Latest reply on Mar 7, 2015 1:05 PM by MichaelF_56

    [BCM20636S] WP control of internal EEPROM and 10k pull-up on P1

    StBa_721356

      We are a little confused about the need of the external 10k pull-up on P1 mentioned in the BCM20736S Technical Reference Manual.

       

      The WP input of the internal EEPROM is active high. So with an external 10k pull-up the EEPROM is write-protected by default.

      But the default P1 GPIO configuration used in all sample Apps is OUTPUT/LOW. So when the device is up-n-running the external 10k pull-up fights against the low signal on P1 and thus introduces a current leak.

       

      In our design we always want to drive WP low for being able to write to the NVRAM without changing the state of P1. So IMHO it would make more sense to either use a 10k pull-down on P1 or to leave P1 floating.

       

      Why would we  need an external 10k pull-up at all?

      What side-effects would be introduced if we would not use the external 10k pull-up?

      Would it be OK to use a 10k pull-down instead of a 10k pull-up?