7 Replies Latest reply on Nov 22, 2018 9:38 AM by ian.cam57_3441841

    GPIF Master Interface with FX3 - FPGA Slave- Bulk-in transfer issue and questions



      I'm trying to develop my own GPIF interface using the FX3 as a master and a Slave FIFO in my FPGA with the HSMC interconnect board, based on the examples in the SuperSpeed Design book and the AN65974 application note.


      First, I'm trying to write and read to/from the Slave FIFO using separated projects.


      • I'm trying to read data from the FPGA, apparently, the DMA buffer where the data it's written get's filled correctly but when I try to take out the data with a bulk-in transfer in the host-pc with the USB Control Center I get the timming error and zero data... Maybe I'm configuring wrong the Endpoint and the USB consumer socket for that DMA Channel (it's configured in AUTO mode), how's the connection of that USB consumer socket with the Endpoint-in that host-pc is getting data from? Any help?


      • Also, seems like the writing process (getting data from the host and write it in the FPGA) is okay, but in the examples of the book is written that drive a GPIO signal takes two clock cycles, so I have to wait two cycles to drive data after driving or assert the WR signal, using  the SignalTap-logic analyzer tool of Quartus it seems this latency does not exist and I lost the first two data words, why?


      • What's the best manner to drive the clock signal from the FX3 to the FPGA?


      Thanks for your attention!