1 Reply Latest reply on Oct 17, 2018 12:43 AM by GeonaP_26

    FM4: Minimum compare clock cycle of ADC

      Hello support team,


      I want to know the minumum compare clock cycle vallue for the ADC of the MB9B568R device.

      The datasheet 002-04864_MB9B560R_Series_32_ARM_Cortex_M4F_FM4_Microsontroller.pdf describes
      on page 144 in the table the value range from 50…1000 ns (AVCC < 4.5V):


      In contrast to that range, the annotation *1 mentions a minimum value of 350 ns:


      Which value should be configured as the correct minimum for reliable ad conversions?

        • 1. Re: FM4: Minimum compare clock cycle of ADC

          The relation between Compare time and Compare Clock cycle is;

                        Compare time (Tc) = Compare Clock Cycle (Tcck) × 14


          For AVCC ≥ 4.5 V, minimum Tcck is 25 nS. Thus, minimum Tc turns out to be 350 nS (14*45 = 350 nS).


          Hope it clarifies your query. Please ensure that sampling time and compare clock cycle meet the electrical characteristics of the A/D converter.

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