As per my understanding, you are facing some issue with the Verilog model of our device S34ML04G2. Could you please attach the waveforms showing this issue?
Thanks and Regards,
Here are waveforms.
To shorten waveforms, I reduced data latch cycle (2112 to 4).
*As I mentioned on my first post, I reduce memory amount of device by changing parameter for simulator memory allocation reason.
I am going to make verilog code for FPGA that interfacing S34ML04G2.
So, I am evaluating your verilog model for my first step.
I am facing issue with cache program command.
First attempt of cache program:
On this attempt, device goes busy state in tWB, it seems to be consistent with datasheet.
Subsequent attempt of cache program (continue):
On these attempts, device will not go busy state until after about 700 us.
I think this behavior is inconsistent with timing chart on datasheet.
(command, address, data cycle)
(on negedge of READY, cursors are same position)
Last attempt of cache program (end):
almostly same to preceded attempts.
I want to know those behavior are same in actual device, or not.
If not, I want to simulate typical tCBSYW case. How can I do ?
Thank you and best regards,
実際の動作であれば、データシートの通り、最後のコマンド10h入力後、tWB = max 100 ns以内にBusy状態となるはずです。