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Hi,
On board, FX3 main clock is supplied by external 19.2MHz crystal and FSCL[2:0] is connected to gnd to select 19.2MHz crystal.
Want to configure FX3 as master and generate clock for slave FPGA on PIN J6(GPIO[16]).
1. How to set GPIF output clock frequency?
2. Once it's set, all GPIOs are working at this clock frequency?
Thanks!
Solved! Go to Solution.
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Hello,
- To set the GPIF II output clock frequency, use the CyU3PPibInit() API along with the required CyU3PPibClock_t structure.
- GPIO 16 is either PCLK/CLK pin depending on whether it is configured as GPIF II master or slave. The clock frequency of operation of other GPIO pins are configured using the CyU3PGpioInit() API with the required CyU3PGpioClock_t structure.
Best regards,
Srinath S
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Hello,
- To set the GPIF II output clock frequency, use the CyU3PPibInit() API along with the required CyU3PPibClock_t structure.
- GPIO 16 is either PCLK/CLK pin depending on whether it is configured as GPIF II master or slave. The clock frequency of operation of other GPIO pins are configured using the CyU3PGpioInit() API with the required CyU3PGpioClock_t structure.
Best regards,
Srinath S