1 Reply Latest reply on Oct 4, 2018 7:50 AM by SrinathS_16

    Provide data to Slave FIFO by CPU in auto in mode



      I am very new in this topic. I wrote a code that use FIFO slave auto in mode and it will get data from FPGA. The FPGA code is not ready yet, however I want to test the transfer. Can CPU provide data for slave fifo in auto in mode? OR is any solution to test this? I attached my code.


        • 1. Re: Provide data to Slave FIFO by CPU in auto in mode



          To test the functionality of the firmware, you can perform the following.

          - Assert the SLWR# pin.

          - Connect the FIFOADR[1:0] pins as per the endpoint. As per your firmware, connect these pins to GND to select endpoint 2.

          - Change the IFCONFIG register to use the internal clock of FX2LP.

          - Use the Cypress USB Control Center to read data from the endpoint 2. FX2LP samples the FD lines and sends the data to the host. If nothing is connected to the FD lines, Control Center reads 'FF's.


          Best regards,

          Srinath S