3 Replies Latest reply on Dec 4, 2018 4:35 AM by srnt

    FX3 GPIO Clocks

    user_455868498

      What are the constraints on FX3’s GPIO clocks. There appear to be system constraints when the maximum 100MHz is selected for GPIO on FX3. At what frequency do the constraints start?

       

      I'm posting this question for a customer to see if there's an easy fix before I dig into the issue. I've found similar issues with GPIO clocks on PSoC 6; but not sure how close the PSoC 6 core is to FX3 or HX3.

       

      G

        • 1. Re: FX3 GPIO Clocks
          srnt

          Hello G,

           

          Please mention if you are planning to use the GPIOs as part of any of the peripheral blocks or as a simple/complex GPIO pin.

           

          FX3 GPIF II clock frequency has got a constraint that the SysClk frequency should be 400MHz in case the PCLK is to be used at 100MHz. Kindly, let know what is the constraints that you are referring to.

           

          Best regards,

          Srinath S

          • 2. Re: FX3 GPIO Clocks
            user_455868498

            Srinath

             

            Thanks for the quick response on your part. I apologize for the delayed response on my part.

             

            I'm interested in both use cases for GPIOs:

            - As part of any peripheral block

            - As simple GPIO pin

             

            In the case of GPIF II clock frequency constraint - at what specific frequency does the constraint apply? I've read some limits at 70MHz, others starting at 80MHz.

             

            Are there any similar constraints for simple GPIO pins?

             

            Section 3.6.6 'GPIF II' of FX3 Programmers Manual has two comments that suggest resource limiting features relying on "Edge Placement" and "shared with other interface modes":

            - A deeper pipeline designed for substantially higher speed (more than 200 MHz internal clock frequency - “Edge Placement Frequency")

            - High frequency I/Os with DLL timing correction (shared with other interface modes), enabling interface frequencies of up to 100 MHz.

             

            Are these comments eluding to constraints?

            Is there any more detail available that describes specific constraints associated with GPIO features?

             

            I appreciate your insight. Simplifying the use of part functionality increases usefulness.

             

            G

            • 3. Re: FX3 GPIO Clocks
              srnt

              Hello,

               

              When the GPIF II interface is running at 100MHz, it is recommended to set the setSysClk400 parameter to CyTrue. This is because the DMA clock would be running at a lesser frequency than the GPIF II interface clock if the FX3 master clock is not running at 403.2 MHz and the GPIF II interface is running at 100 MHz. Please look at the below table.

               

              FX3 CPU Clock = FX3 Master Clock/(Divisor)                        ; Minimum Divisor – 2

              FX3 DMA Clock = FX3 CPU Clock/(Divisor)                           ; Minimum Divisor – 2

               

              FX3 GPIO Fast Clock = FX3 Master Clock/(Divisor)               ; Minimum Divisor – 2

              FX3 GPIO Simple Clock = FX3 GPIO Fast Clock/(Divisor)     ; Minimum Divisor – 2

               

              Clock

              Maximum Frequency (MHz)

              setSysClk400 = true

              setSysClk400 = false

              FX3 Master Clock

                      403.2

              384

              FX3 CPU Clock

                      201.6

              192

              FX3 DMA clock

                      100.08

              96

              FX3 GPIO Fast Clock

                      201.6

              192

              FX3 GPIO Simple Clock

                      100.08

              96

               

              Simple GPIOs use the FX3 GPIO Simple Clock to sample the pins and hence can operate at a maximum of 100.08 MHz. Complex GPIOs use the FX3 GPIO Fast Clock and hence can operate at a maximum of 201.6 MHz.

               

              Best regards,

              Srinath S