1 Reply Latest reply on Oct 1, 2018 11:42 AM by DaGi_900591

    DMA TD completion too early




      I have a simple 500kHz clock connected to a DMA component. This is triggering a peripheral-to-memory transfer (from a status register, if that matters) with a request size of 1 and transfer count of 64, and every TD has DMA__TD_TERMOUT_EN set because I want to be told each time one completes.


      The clock is triggering drq every 2us, so I'd expect to see a nrq every 2*64 = 128us. But I'm not. I'm getting one every 8us, with obviously hilarious results.


      Does anyone know what might be causing this?


      My project is here: fluxengine/FluxEngine.cydsn at master · davidgiven/fluxengine · GitHub


      However, the function which is doing DMA setup is here: fluxengine/main.c at 4e19882d76d90823bed487e7903d0bc87162aa97 · davidgiven/fluxengine · GitHub

        • 1. Re: DMA TD completion too early

          Fixed: I was using CY_DMA_TD_AUTO_EXEC_NEXT, when I shouldn't have been.


          So it seems that AUTO_EXEC_NEXT does not mean 'I have multiple TDs in a chain which need to seamlessly flow into each other'. What it means is 'Automatically trigger a DMA transfer for the next TD when this one completes', i.e. if you want continuous memory transfers as fast as possible. As my transfers were all externally triggered via the drq line, this was causing really weird stuff to happen.