8 Replies Latest reply on Oct 14, 2018 12:41 PM by TeMa_1467596

    SMIF on PSoC6 CY8CKIT-062-BLE


      I have added a SMIF component to my project and I'm trying to set it up to run from the cm0+ core.  The SMIF interrupt is assigned to the cm0+


      I am trying to follow the component datasheet.  It says to paste in code from page 3 but that  code contains errors that are "use of undeclared identifiers" (see picture below).  I am also looking at the code example CE220823 but that seems very different to the datasheet instructions.


      I think I need to run in memory mode, not normal mode, as I want to issue commands to read and write pages, erase sectors, and clear the entire memory - is that right?



        • 1. Re: SMIF on PSoC6 CY8CKIT-062-BLE

          Hello Ted,


          Please follow CE220823 for using the external memory. The datasheet code is a bit old, I will file a defect ticket to get it fixed (either point to the CE or update the code).


          To your question, you need to run it in MMIO mode not Memory/XIP mode. The MMIO mode lets you use the QSPI block as a peripheral talking to an external device (like how you use SPI to talk to an external memory). The memory or XIP mode configures the QSPI block to respond to AHB bus transfer requests. If you have already mapped the external memory to a XIP address space (0x18000000 to 0x1FFFFFFF), then any data/code requests in that region automatically gets serviced by the QSPI block. However, if the block is not configured for proper read/write commands, these access will result in bus faults. Note that external NOR/NAND flash do not support byte writing (they usually require a block-erase followed by block-write command for properly writing). These sort of write transfers are not supported in the memory/XIP mode. Only byte-wise read and byte-wise write commands can be used in memory/xip mode. In the MMIO mode, you can do all that you mentioned.


          For setting the mode, use Cy_SMIF_SetMode() API. The "CY_SMIF_NORMAL" parameter puts it in MMIO mode and the "CY_SMIF_MEMORY" parameter puts it in memory/XIP mode.


          Let me know if this helps or if you have more queries.



          Meenakshi Sundaram R

          1 of 1 people found this helpful
          • 2. Re: SMIF on PSoC6 CY8CKIT-062-BLE

            Thanks Meenakshi, I'm going to try this out today.


            [EDIT] I've read through CE220823, the PDL documentation, and I looked again at the datasheet examples.  I'm struggling as these all seem to be biased towards Memory/XIP mode.  I have (automatically generated I presume?) files called:







            CE220823 has these files plus additional files called





            Which include functions like WriteMemory() that are used in the CE220823 example m4 code but, unless I move or add these files to my project, I won't have these functions available to me; what do I do?


            FYI I am very familiar with the S25FL512S device and have written a complete system that uses single channel SPI to control it doing sector erases and page writes.


            Is there an example somewhere that will give me the basic steps that I need to follow to use the files that are generated by including the SMIF component in my project to:


            1. Initialize the memory
            2. Erase the entire memory
            3. Erase a sector
            4. Write pages to specified page numbers (or smaller byte sequences to specific addresses)
            5. Read pages from specified page numbers (or smaller byte sequences from specific addresses)


            This is getting time-critical for me now.


            Thanks in advance,



            • 3. Re: SMIF on PSoC6 CY8CKIT-062-BLE

              I've been trying to get this working today by copying chunks of code across from CE220823 and I've run into an issue that I think is because the example code is running on the m4 core and I am trying to make it run on the m0p core.  I copied the ISR code into my main_cmp0p.c file but it gives me a warning that says...


              implicit conversion from enumeration type 'cy_en_intr_t' to different enumeration type 'IRQn_Type'


              and I get another warning with exactly the same text when try to I enable the SMIF interrupt as follows



              when I right click and go to the definition of the cy_stc_sysint_t, I see that it seems to think that it's NOT on the m0 core as the line with cm0pSrc is grayed out on cy_sysint.h...


              I think that the issue is that I need to tell the ISR that it's on the m0p core but I can't figure out where/how to do this.


              Any ideas on how to fix this?


              FYI, I copied and added in the smif_mem.h and smif_mem.c files from CE220823 so I could use the APIs in that code.

              • 4. Re: SMIF on PSoC6 CY8CKIT-062-BLE



                CM0+ supports only 32 interrupts. Hence all the system interrupts a mutliplexed at each of the 32 CPU interrupt. For you to successfully map a system interrupt to a CPU interrupt, you need two values -

                1. CPU interrupt mux - This is what should be passed to "intrSrc" parameter and it is usually in this form "NvicMux0_IRQn"

                2. System interrupt mapped to the CPU mux - This is what should be passed to "cm0pSrc" parameter and this is the actual system interrupt you want to map


                For your case you can use the below examples -

                cy_stc_sysint_t smifIntCfg= {

                        .intrSrc = (IRQn_Type)NvicMux9_IRQn,

                        .cm0pSrc = (cy_en_intr_t)smif_interrupt_IRQn,

                        .intrPriority = 3



                Note that CM0+ has only 4 priority levels (0-3) compared to CM4, which has 8 priority levels (0-7). Hence make sure the priority set is within the M0+ limit.


                Hope this helps.



                Meenakshi Sundaram R

                1 of 1 people found this helpful
                • 5. Re: SMIF on PSoC6 CY8CKIT-062-BLE



                  Thanks for helping on a weekend, your suggested code made the first yellow triangle go away but the line to enable that interrupt is still giving the same warning...


                  This is the original line...




                  and that has the warning triangle.  I tried




                  But that was the same.


                  I have read AN217666 but it doesn't go into enough detail on how to define and enable cm0+ core interrupts.


                  If you're around, can you please help solve this?

                  • 6. Re: SMIF on PSoC6 CY8CKIT-062-BLE

                    You need the below code -




                    Again, CM0+ does not support more than 32 interrupts. smif_interrupt_IRQn is a system interrupt not M0+ interrupt. The NvicMux0_IRQn are the CPU interrupts that is used with NVIC_EnableIRQ API.



                    Meenakshi Sundaram R

                    1 of 1 people found this helpful
                    • 7. Re: SMIF on PSoC6 CY8CKIT-062-BLE

                      Thanks, in my case it ended up as...




                      Now I'm going to see if it works.


                      [EDIT] Tested the read functionality and it's working so I suspect that I'm good to go.  Thanks so much for you assistance Meenakshi

                      • 8. Re: SMIF on PSoC6 CY8CKIT-062-BLE

                        Now I can read from the S25FL512S but I'm confused on how to control the addresses within the device.  When I perform a read of 16 bytes with this command (copied from CE220823 except that I changed the 256 to 16 bytes)...


                        ReadMemory(SMIF_1_HW, &SMIF_1_context, rxBuffer, 16, extMemAddress);


                        It returns...


                        SMIF operation in quad mode

                        Received Data: 0x2


                        Quad I/O Read (QIOR 0x38)

                        Received Data: 0x80 0xB5 0x00 0xAF 0x00 0x22 0x01 0x21 0x07 0x48 0x00 0xF0 0x11 0xF8 0x0A 0x20


                        And the fact that those first bytes are not blank suggests that it's reading from the OTP area in the memory and I need to be working in the main area which should be all 0xFF


                        Can you help me out with the commands you suggested (or the ones in CE220823) to show how I can be sure what address I'm reading/writing to in the S25FL512S memory map?




                        [EDIT] Tried on another board, the data read is 0x00 0x01 0x02 0x03 etc and I think that means that it's been written to by one of the sample programs.  It may well be that the answer to my question above is mainly that the 3-byte address is the address into the device but that means that I can only get to 16,777,216 addresses and I should be able to get to 64 million so maybe that's something to do with the base address and I'd still like to clarify how that works using SMIF.