7 Replies Latest reply on Sep 24, 2018 1:15 PM by user_49271930

    Can PSOC 5LP DMA generate a signal after each transfer (not finishing TDs)

    user_482916809

      Dear all,

       

      I am wondering Can PSOC 5LP DMA generate a signal after each transfer (not finishing TDs)? I understand that NRQ can generate a signal of two clock cycles after the TDs is finished (I chained 16 TDs). I am asking because there are two DMA channels in parallel sharing the same spoke (DAC). They may or may not be at the same rate. I want to know when each transfer is done so I can align the signal. The master clock is 78MHz.

       

      The signal I am trying to alian is the trigger out signal. So I generate a waveform from flash through dma to DAC and output to a GPIO. I want to generate a trigger signal which is aligned with the waveform to another GPIO. What I did is that I user a counter, and route the drq signal and count of the trigger together. I set the period of the counter to the number of points that DAC will output and compare threshold of the counter to be half of the number of the points in DAC. I then use the compare out as the trigger signal. I can get the trigger aligned when 2 DAC channel are used at maximum speed of 1Msps. When I set the update rate of both channel to 2Msps, the output signal in DAC and trigger are still correct in timing. However, the alignment is lost, and timing difference is keep shifting. In update rate between 1Msps and 2Msps, each time after the sequence is downloaded via USB, there is a chance that the alianment will miss but not each time.

       

      I suspect it will be better if I can have access to the signal that each DMA transfer finishes as that will the be the exact time that I want to count in the counter.

       

      Best,