Please share the project to troubleshoot.
I can create a small sample project where the circuit works wonderfully. Could it be that my problem comes from an external component on my design? On the same ground there is another motor. For example, on the VCCD pin I see every circuit of the "Clock_sig" with a short oscillation. As soon as the motor is running I measure bigger disturbances on it.
What I ask myself is how I can solve the problem in a structured way. I would intuitively try to change a few capacities around the PSoC, but that would be very arbitrary.
How do I make Custom Logic more stable against disturbances?
1. Stabilize power supply
2. Stabilize power supply
3. Stabilize power supply
Avoid open (unconnected) pins. Set them to VCC or GND internally.
Stabilizing is easier said than done. Is there a special supply port that is responsible for custom logic and needs to be better stabilized?
Since the processor has neither resets nor any other problems, I think it is possible to tackle the problem more specifically.
An additional D-Flipflop in front of the two originals has already helped. From a clockdomain transition this should always be necessary, as I noticed.
I would suggest to check all supplies with a scope set to AC measure and look for spikes when motors are running.
Afaik there has been no chip internal crosstalk reported yet, so I assume some external causes.
Please attach your project schematic (preferably in .pdf format). I will check it and let you know Cypress' suggestions. Also please tell about the frequency of the glitch you are observing and what are the various scenarios those will influence the glitch.