4 Replies Latest reply on Oct 16, 2018 5:11 AM by VasanthR_91

    Delta Sigma ADC configuration and operation



      I would like to use the delta sigma ADC from 5LP in one of my application and I have some questions:

      1.     I intend to monitor 3 single-ended signals using the inherent analog multiplexer and the delta sigma ADC available. The monitored signals range from 0 to 5.15V and I need to adapt my input voltage to the ADC input ranges available in datasheet using a voltage divider alongside a filter capacitor. For single ended operation I thought to go with the 0-2.048V range, hence I need to divide my input signal by 2, approximately (I do not have a very stable Vdda available on my board therefore the Vssa to Vdda option does not fit my needs).

            According to the datasheet this option sets automatically the buffer gain to 1, which normally would clip the input voltage range to both upper and lower rails. However the datasheet also states that the single-ended option will bypass the low side buffer.

            Does it mean than when configured as single-ended the input signal will not be affected by the lower voltage limit of the buffer, VOL?


      2.     I did not found any information about the leakage current of the ADC pin and maximum allowed current into the ADC pin (or GPIO as a matter of fact), inside the document. The leakage component will affect my readings due to the voltage drop across the series external resistor.


      3.     Another point concerns the external capacitor – is it ok if I foresee a filter capacitor 1000 x the value of the hold capacitor? The cut-off frequency of the external filter is not a big concern as I am monitoring some rather sluggish signals.


      4.     The last point that I am interesting in: could I use the differential mode configuration to measure single ended signals?

           The datasheet states that in differential mode I can tie the negative input to 2.028V and obtain a usable input range between 0 and 4.096V. Does it mean that even if in differential mode I can monitor a single-ended signal ranging from 0 to 4.096V? This would be more appropriate for my application as it is closer to the input signal range. Please let me know if possible!

           Also, I presume there is no bypass of the rails when configured as differential, so for monitoring low voltage signals (under 100mV) is should bypass the buffer.


      Many thanks for your support,


        • 1. Re: Delta Sigma ADC configuration and operation

          Hello Florin,





          This is the internal structure of the buffer(refer PSoC 5 architectural TRM). These buffers are independent of each other. On single ended mode the low side buffer is bypassed and grounded. But that does not limit lower voltage limit of the buffer as they are independent.




          This information is from the datasheet. Please check the GPIO DC specification section.

          The absolute maximum current the device can sustain is

          These are the absolute maximum values, crossing this will permanently damage the device.


          3. There is no sample and hold block in delta sigma adc architecture. Could you please let me know which hold capacitor are you talking about ?


          4.Yes you can do this. In this case your external signal ground and PSoC ground should be connected or at the same level.


          You have an option to bypass the buffer on the component. This can be chosen on differential input.



          Best Regards,


          1 of 1 people found this helpful
          • 2. Re: Delta Sigma ADC configuration and operation



            Thank you for your feedback!


            Regarding Q3 I was reffering to Input capacutance table in the delta sigma ADC datasheet (page 42). Could you explain what these values are referring at?


            Thank you,


            • 3. Re: Delta Sigma ADC configuration and operation



              Could you give me the link to the document that pose the current limits for the GPIOs (i.e. the one containing the images in your first answer)? I searched for it, but the current ratings that I've found for PSoC 5LP are 4mA sourced and 8mA sunk (http://www.cypress.com/file/45381/download ):

              or (http://www.cypress.com/file/44581/download ):

              Also, could you let me know the meaning of the Input capacutance table in the delta sigma ADC datasheet (page 42):

              Thank you,


              • 4. Re: Delta Sigma ADC configuration and operation

                Hi Florin,


                1) Please check the (http://www.cypress.com/file/45906/download ) 11.1 Absolute Maximum Ratings. The device can withstand the current, without damage. Even then going to the boundary is not advisable. The source and sink currents  you have specified are related to the digital pins specification which meets the Voh and Vol specs. But there are other limitations you need to worry about. Total source+sink current should not exceed 100 mA for any VDDIO quadrant.


                The capacitance table is for the modulator part of the ADC, which is a switched capacitor design. When you said the hold capacitor, I was thinking whether you thought the design is similar to SAR ADC with sample and hold block. The modulator comes only after the buffer(unless bypassed). Now regarding your question, connecting the 1000xcapacitor might not be a problem unless your signal source does not have any problem sourcing it. The startup and delay for correct results might be higher, which you have to take care in your design. You can check whether the results are coming properly without the capacitor first.


                Best Regards,