Thank you for your help.
I can't find description about input step characteristic in the TRM.
Excuse me, please tell where is it.
Please tell additional question.
The customer thinks that the following data may be what he needs.
The data is described on "001-84932_PSoC_5LP_CY8C58LP_Family_Datasheet_Programmable_System-on-Chip_PSoC_Datasheet.pdf".
I think the parameter and condition are as shown below figure.
If yes, please tell two pin values.
If no, please give more information about the Specifications.
The comparator output is digital in nature, thus the step follows hfclk and the rise and fall times of a digital signal.
This comparator response time in the Table 11-33 were measured by device characterization (i.e. bench test) as Note, and they can be only measured at external pin-to-pin.
Basically, Comparator response time is measured as follows:
=(Input to Output delay with comparator) - (Input to Output delay with comparator bypassed )
Vinp is fed with a square waveform with offset of Vref , pk-pk voltage equal to the overdrive condition. Vinm is fixed at Vcm
Vout waveform will be same as Vinp but delayed due to Tresp and its pk-pk is equal to the VDD of the IO domain in which the output pin is powered.
The timing image would be like:
Thank you for your answer.
I understood it.
Do you need any other clarification/support for this thread?
If yes, it would be appreciated if you make it clarified again.
Thank you very much.
Using direct communication to Yoshioka-san,
I have confirmed the information that the customer wants does not exist.
So, I don't need any other information/clarification/support.