This content has been marked as final. Show 2 replies
Hi I am working with PSoC 5 development board 059, I am trying to have an UART or more that are capable of switching their baud rate dynamically.
My master clock is set to 24 MHz, if I divide the master clock by 96, i get the 31250 baud rate, but to get 115200 it is not an even clock division -> 24 MHz / (115200 *8) =
26.041. So if I set the clock divider to 26 this would mean an overall error of 0.16% (Error/RealValue)(0.041 / 26.041) I might think this is enough, but I don't know.
Does anybody knows which is the accepted clock error on UART??
Thanks in advance, José Manuel Romo
Edit: I tested, 115200 works, but does any body knows which is the overall error accepted for clock UART devices?