3 Replies Latest reply on Sep 11, 2018 9:53 AM by BoTa_264741

    Running SAR ADC when CPU is running at 80MHz


      I'm trying to find a confuguration where I can run the CPU at maximum speed (80MHz on CY8C5888AXI-LP096 in this case) and also using the SAR_SEQ component.


      Setting the Master clock to 80MHz (with XTAL) will result in an ADC clock > 18MHz = error


      I tried using an 18MHz XTAL (Master clock 80MHz) = "Error in component: ADC_SAR_Seq_1_SAR. Divider of SAR ADC clock must be 2 or greater when source clock frequency is between 15 MHz and 40 MHz.", setting the Master clock to 72MHz solves this error so the error test is porabably some indirect error.


      Does anyone have a working clock configuration to acheive this?


      Thanks for any comment on this.