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Setting the Master clock to 80MHz (with XTAL) will result in an ADC clock > 18MHz = error
This is due to a too high sampling frequency. With one channel the sampling can be as high as 1MHz, with two channels only 500kHz.
I get it, I can select a lower sampling frequency even if the clock is higher than the maximum input clock to make it lower. A bit strange that this is not adjusted in the SAR_SEQ UI instead. It is confusing when the component always shows what it "would be" if the input clock is 18MHz, and then some recalculated sampling rate.
Please check threads below re: overclocking ADC_SAR. The idea is to cheat ADC by preventing it from calculating the clock frequency. If clock connected directly, there is API to obtain its frequency, when some other element is introduced in-between, the frequency is not available and the error is not produced