The attached project implements a Manchester Decoder in hardware using the PSoC Smart IO and a PWM component. The technique used is similar to what is shown in: http://www.cypress.com/documentation/application-notes/an2358-manchester-decoder-using-psoc-1
The Smart IO block is used to create both the XOR gate and DFF while the PWM acts as the delay counter. Using the Smart IO allows the design to off load logic from UDBs or implement a hardware solution in lower end devices without UDBs, such as the P4000s family.
