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Typical HyperBus controllers support features which automatically splits one lengthy operation to multiple ones. According to the MCU datasheet you attached, the "Communication regulation features" in page 532 seems to be that.
I would show you a calculation example here. I assume that the MCU and the HyperRAM configurations like below. Please see Figure 75 in the MCU datasheet for the HyperBus protocol.
CS#=L to 1st CK: 1 CK cycle
last CK to CS#=H: 1 CK cycle
Command cycles: 2 CK cycles
Latency Count 1: 6 CK cycles (default)
Latency Count 2: 6 CK cycles (default)
Therefore, total 16 cycles are required excluding data transfer cycles.
In case the HyperBus operates at 8MHz, number of CK cycles allowed during CS#=L is 4us / 125ns = 32.
You can use 32 -16 = 16 cycles (32 bytes) for data transfer.
Dear Takahiro ,
Thanks for your help .
"Communication regulation features" seems to be perfect setting for this issue .
1. Please confirm , as per your calculation for 8MHz clock , we need to set max 5 count in CSBOUND register it is equal to (2^CSBOUND) . 2^5=32 .
2. After setting proper value in "Communication regulation features" / CSBOUND register , can we use this external Hyperram for saving RTOS TASK Table ? Is it safe ?
3. Is there any application limitation ( other than speed ) while using Hyperram same as internal RAM ?
Thanks for your reply.
#1: CSBOUND=5 looks correct to me. If possible, please confirm with ST as well.
#2 & #3: From software perspective, you can use HyperRAM as internal RAM because the HyperBus controller abstracts the hardware differences between them. In addition to the CSBOUND register in MCU side, you may need to set proper value to Configuration Register in HyperRAM. Please refer to the HyperRAM datasheet about it. Especially, in case your MCU has cache, the Wrapped Burst Length must be same as size of one cache line.
Dear Takahiro ,
thanks for your reply . I just confirmed with ST FAE & CSBOUND is the setting required for given issue .
Also while reading Datasheet of Hyperram , under section 3.3 Read Transactions & 3.4 Write Transactions with Initial Latency
"However, some HyperBus devices may require a minimum time between the end of a prior transaction and the start
of a new access. This time is referred to as Read-Write-Recovery time (tRWR). The master interface must start driving CS# LOW
only at a time when the CA1 transfer will complete after tRWR is satisfied."
1. In above para i am not able to understand what is meaning of "The master interface must start driving CS# LOW only at a time when the CA1 transfer will complete after tRWR is satisfied." ? is it mean master should low CS pin after CA1 transfer & tRWR time ? if yes then how communication can start before that as CS pin will high before CA1 & tRWR ?
Thanks for confirming with ST about CSBOUND.
Regarding tRWR, the description means that the master interface should keep CS pin HIGH for a certain period of time that makes CA1 transfer occurs after the tRWR. It assumes that the time between CS# LOW to CA1 is fixed so timing adjustment need to be done by CS# HIGH period.
In the ST datasheet, TRWR bit in the OCTOSPI_HLCR register seems to control the tRWR directly.