In PSoC3/5, each UDB block contains a Control Register and a Status Register. By using DMA, Control/Status Register can be use to output/get parallel data conveniently. If the parallel bus width is less than or equal to 8-bit, it is easy to deal with. But when parallel bus width is between 9-bit to 16-bit, some points need to be paid attention when implement the design.
This document documents how to realize 9 to 16 bits parallel data transfer use Control/Status Register. The relationship between UDB location and Control Register (Bx_UDBxx_CTL)/Status Register (Bx_UDBxx_ST) base address is also tested and listed..
Linking two 8-Bit Registers to a 16-Bit register
As we all know, the width of a Control/Status Register is 8 bit. If we want to transfer a 9 to 16 bits parallel data, we need to link two Control/Status Registers together to a 16-bit register. Actually, when we add two Control/Status Register components in the schematic, Creator can link the two 8-bit register to a 16-bit register automatically, the generated register name is stored in cyfillter.h. For example, I add two Control Register components in the schematic, after build the project, below contents will be generated in cyfillter.h. It is the generated 16-bit control register, it connect register B1_UDB10_CTL and B1_UDB11_CTL together.
#define Control_Reg_1_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
In default, when we add two Control/Status Register components in the schematic, Creator will allocate two registers which have continuous base addresses to these two components. This can promise the generated 16-bit register is usable. But in a real design, we prefer to lock the assign relationship between the two Control/Status Register components and two Bx_UDBxxCTL/ Bx_UDBxxCTL registers which have continuous base addresses. Only by doing this, we can promise the project works well always when adding other UDB based components in the schematic. It is lucky, Creator supplys feature to allow us define how to allocate the UDB location to relative component.
UDB Location Allocation
Creator Supplys Directive Editor which is used to add, remove, and edit directives. We can add Directive to define the allocation relationship between UDB blocks and Control/Status Register component, like below:
The Component (Signal) Name can be found in *.rpt file of the project, “ForceComponentUDB” directive type should be cheese, “Directive value” point to which UDB block should be assigned to the component. Follow the above directives, the two control registers belongs to UDB(0,0) and UDB(1,0) will be allocated to Control register component Control_Reg_1 and Control_Reg_2 respectively. So, by using the above method, we can lock the assign relationship between two Control/Status Register components and two Bx_UDBxxCTL/ Bx_UDBxxCTL registers which have continuous base addresses.
UDB location and Control/Status Register Address
Which two UDB blocks have continuous base addresses Control/Status Registers? With this problem in hand, I tested all the UDB location in Directive Editor, tests results as follow:
So, when you want to realize 9 to 16 bits(or even higher) parallel data transfer use Control/Status Register, we can simplify it to steps below:
- Add two Control/Status Register components in the Top Design.
- Use Directives to define the assign relationship between two Control/Status Register components and two Bx_UDBxxCTL/ Bx_UDBxxCTL registers which have continuous base addresses.
- Build and project and find out the connected 16-bit register in cyfitter.h
- Add DMA component and configure DMA Source/Destination address as 16-bit register address get in #3.
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thank you for detailed explanation. Would be worth to make a KBA from it.