How to reduce ripples with swapped clock?

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FuKo_2271141
Level 1
Level 1

Hi, I'm emulating neural cells with PSoC1.  The chip packs two cells, each with two SC blocks.

One cell, with two blocks connected by external wiring, works fine, as shown in the following

scope image, with stable baselines:

clock_norm.JPG

But, the other cell shows:

clock_swap.JPG

Problem is the blue baseline including ripples of clock frequency (two spikes vs three above are OK).  The

blue block is fed directly by another block, and is configured with "ASign: Pos", so with "ClockPhase: Swap"

(I understand that non-inv amp gets input at phi 1, then not consistent with the feeding amp with its output

active at phi 2).  Sure, external connection will solve the problem, but no routing resource.

Any hint is welcome.

Fumi

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Hello Fuminori-san,

I could not understand the implementation correctly. I wish to make one observation here. Once, the output of the SC Block is connected to Analog Output Column, there should be no ripples.

Thanks, and best regards,

Sampath Selvaraj

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14 Replies
SampathS_11
Moderator
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250 sign-ins 250 solutions authored 5 questions asked

Hello Fumi-san,

It will be best if you attach PSoC Chip View diagram, and explain more about what the SC blocks are doing. It would be best if you attach the PSoC project. I would be able to ask you appropriate questions.

Thanks, and best regards,

Sampath Selvaraj

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Hi, Mr?. Sampath

Thank you very much for your prompt response.

On (2018/08/23 15:43)

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Mr. Sampath

>> the whole project is attached.

I forgot an important info: two external wirings, from P0[5] to P2[3]

and P0[4] to P2[2], are necessary to complete circuit. The problematic

SC block pair is ASC10 and ASD11, with ASD11 output with ripples (ASD22-

ASC23 pair works fine).

Regards,

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Hello Fuminori-san,

Kindly let me know why you have used PGA_1 for ASC10/ASD11 pair. DAC6_1 Clock Phase is set to swapped, and DAC6_2 Clock Phase is set to normal. Why is this so?

I request you to kindly bear with me, since I am not yet having full understanding of the implementation of function you have implemented in PSoC.

Thanks, and best regards,

Sampath Selvaraj

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FuKo_2271141
Level 1
Level 1

Hi, Mr. Sampath.

Thank you for your questions.  Sorry for asking about very special usage.

PGA_2, not 1, for ASC10/ASD11 is inevitable: if not used, ASD11 BMux cannot be driven by ASD11 output (self feedback).

Swapped clock for DAC6_1 is because ASign of ASC10 is Pos (if configured non-inv, A is captured at phi 1).  Actually, if clock is set Norm, the pair do not work (two DC voltages only).

Regards,

Fumi

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Hi Fuminori-san,

Can you kindly let me know how to setup this project? I will try to reproduce the issue on my bench.

Thanks, and best regards,

Sampath

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FuKo_2271141
Level 1
Level 1

Hi, Mr. Sampath

Sorry for tedious question.  I already posted my project in .zip two weeks ago.  By unzipping and opening, you can set it up.

Regards,

Fumi

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Hi Fuminori-san,

I was supposed to ask about the hardware setup. Are you using customer hardware or a Cypress kit?

Thanks, and best regards,

Sampath

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Hi, Mr. Sampath

Sorry, you are asking about hardware.  I'm using CY3210, with some external wirings to connect Pxs.

Regards,

Fumi

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Hello Fuminori-san,

I observed the waveforms at P2[2] and P2[4]. The waveforms do not indicate ripples due to the SC Block clock.

However, I am unable to understand what the code does. It would be great if you can give me a line by line explanation, as appropriate.

Best regards,

Sampath

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Hi, Mr. Sampath,

Sorry for delay, because I was out for 1 week (to present another research using PSoC).

Isn't "P2" you mentioned actually "P0"? (P2[4] is not connected to anywhere) Yes, P0[2] and P0[4] are OK. The ripple problem is on P0[5], for the other loop.

Attached please find the commented main.c (but not line-by-line, because macroscopic looks better, especially for assembly part).

  1. Some lines may look peculiar, but they are devised to avoid problems in type conversion.

Regards,

Fumi

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Hi, Mr. Sampath,

Additional info:

1.Changing the chip does not change the situation.

2.Regarding "ripples of clock frequency":

  So far, CLK_CR0=0, which means analog clock is VC1.  If I double VC1 frequency in the global resource, ripple frequency gets twice and amplitude is halved.

My consideration:

Waveform of ripples is triangular, meaning square wave (of clock) is injected into the inv. input of OP amp. and integrated.  I found ripples in other OP amp outputs, very small though.

Clock waveform on p. 374 of Tech. Ref. Manual shows phi1 with 1 longer than phi2.  If they are swapped, is there any effect of this asymmetry?

Regards,

Fumi

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Hello Fuminori-san,

I could not understand the implementation correctly. I wish to make one observation here. Once, the output of the SC Block is connected to Analog Output Column, there should be no ripples.

Thanks, and best regards,

Sampath Selvaraj

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Mr. Sampath,

Sorry, I missed your last post after several weeks.

|> the output of the SC Block is connected to Analog Output Column, there should be no ripples.

Understood.  But if blocks are connected directly, as in the case of ACB01 drives BMux of ASD11, ABus is not used, right?   My circuit is very packed and does not have margin to use ABus for such connections. 

OK.  If there is no way of reducing ripples in direct connection, I will accept the situation and proceed.  Thank you very much for many replies over four months.

Regards,

Fumi

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