14 Replies Latest reply on Dec 22, 2018 10:09 PM by FuKo_2271141

    How to reduce ripples with swapped clock?

    FuKo_2271141

      Hi, I'm emulating neural cells with PSoC1.  The chip packs two cells, each with two SC blocks.

      One cell, with two blocks connected by external wiring, works fine, as shown in the following

      scope image, with stable baselines:

      clock_norm.JPG

      But, the other cell shows:

      clock_swap.JPG

      Problem is the blue baseline including ripples of clock frequency (two spikes vs three above are OK).  The

      blue block is fed directly by another block, and is configured with "ASign: Pos", so with "ClockPhase: Swap"

      (I understand that non-inv amp gets input at phi 1, then not consistent with the feeding amp with its output

      active at phi 2).  Sure, external connection will solve the problem, but no routing resource.

       

      Any hint is welcome.

       

      Fumi