The length matching guide lines given in our application note AN211622 (http://www.cypress.com/file/278156/download) is applicable for operating frequency 166 MHz. As you can see on the datasheet (http://www.cypress.com/file/183506/download), our device S70KS1281D support 2 maximum clock rates.
Maximum Clock Rate at 1.8 V VCC/VCCQ = 166MHz
Maximum Clock Rate at 3.0 V VCC/VCCQ = 100MHz
Section "4.2.2 Length Matching" in the application note describes the length matching requirements for above 2 clock rates.
Could you please capture the read waveform when this issue happens and send to us? It will give us a better idea about this issue.
Thanks and Regards,
Is 25mils a reference to 25 millimetres or 25 thousandths of an inch?
We are using 1.8V so running under the 166MHz maximum.
"mils" refers to "thousandth of an inch". 25 mils equal to 0.635 millimeter (mm).
Thanks and Regards,
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Could you change output drive strength via Configuration Register 0 (CR0[14:12]) in the HyperRAM?
Since the S70KS1281 is a dual-die-stack part and you use 2x S70KS1281, you need to change CR0 settings for 4 dies in total.
The word addresses of the CR0 are 0x000800 (first die) and 0x400800 (second die).
Please refer to the HyperRAM datasheet for possible drive strength settings - http://www.cypress.com/file/183506/download
Thanks for the help. We now have the system working. The tip about checking all dies registers is a useful one to note.
We had to set the output drive strength differently (reduced the number of errors). We also had to change the drive strength of our host device (still occasional bit errors over 10s MBytes). The final part of the puzzle was a register in the host device to change the number of delay elements in the RWDS input path.
With this register and its new setting we have a system working at 144MHz with an RWDS to DQ skew of +/-3mm (approx. 20ps difference). I don't think +/-0.635mm is realistic for our design, and I still don't see where the +/-0.635mm is derived from in the timing. I'd like to see the calculation, especially as I can then derate it for 144MHz. I assume it comes from the tDSS and tDSH timing - but that is 450ps at 166MHz?