4 Replies Latest reply on Feb 3, 2015 2:03 PM by jota_1939431

    Power rail requirements on SoC during sleep/HIDOFF?

      Is it possible to power down any of the power rails, ie VDDC/VDDO when the device enters deep sleep or HIDOFF?  If so can the firmware trigger a GPIO to enable/disable an external regulator when switching power modes?  Furthermore, if the design was an SoC where the radio will never be used (consider it a de-featured product where we wish to leverage existing firmware effort), can any of the other RF-related power rails such as VDDIF/VDDFE/VDDVCO/VDDPLL be permanently grounded?

       

      romic_1245456

        • 1. Re: Power rail requirements on SoC during sleep/HIDOFF?

          Hello Andrew,

           

          Is it possible to power down any of the power rails, ie VDDC/VDDO when the device enters deep sleep or HIDOFF?

          [JT] VDDO needs to be enabled to power up a GPIO

           

          If so can the firmware trigger a GPIO to enable/disable an external regulator when switching power modes?

          [JT] - The Internal LDO can actually disable the core and radio to ~0V, but again, you still need 1.8V for GPIO.

           

          Furthermore, if the design was an SoC where the radio will never be used (consider it a de-featured product where we wish to leverage existing firmware effort), can any of the other RF-related power rails such as VDDIF/VDDFE/VDDVCO/VDDPLL be permanently grounded?

          [JT] The core can be set to ~0V, but you still need to wake up using 1.8V GPIO - This rail also powers up the EEPROM or Serial FLASH where your code is stored.

           

          Hope this helps,

          JT MichaelF_56

          • 2. Re: Power rail requirements on SoC during sleep/HIDOFF?

            Hi JT,

             

            I figured as much w/ VDDO but it's still not clear if we can use a firmware-controlled GPIO to enable/disable an external regulator that powers VDDC?  Or do you suggest possibly using the ~1.2V output of the LDO itself to do this?  Or is it best to just stick w/ using the internal LDO to power VDDC despite the higher active source current?

             

            Also, what about all the RF rails (VDD_RF domain in the datasheet)?  Must they be powered even if the radio will never be used?  The above wasn't clear.

             

            Thank you,

            Andrew

            • 3. Re: Power rail requirements on SoC during sleep/HIDOFF?
              MichaelF_56

              Note that you can not turn the radio off.

               

              However, if the application turns off all adv, scans and connections, the RF HW block will not transmit/receive anything.

              • 4. Re: Power rail requirements on SoC during sleep/HIDOFF?

                Hello Andrew,

                 

                You need 1.8V on the GPIO in order to wake up from a GPIO

                The GPIO 1.8V needs to be present before the 1.2V Core and Radio.

                 

                Thanks

                JT