Yes, the leakage current of all the pins will be dependent on the speed mode, including the configuration pins.
In this case, I have further questions:
Data sheet pg. 17/29: Pull-down resistor of greater than 100K is needed for Individual mode
So maximum -10uA of input current, or in another words, 10uA of output current will flow through the 100K pull down resistor to ground?
Is my understanding correct?
Data sheet pg 19/29: Input Low Voltage (VIL) is 0.8V maximum
Under worst case condition when maximum leakage current of 10uA flows through 100K pull down resistor, the 1V (10uA X 100KR) drop on Individual pin (pin 39) might NOT be seen by CY65634 as low under Worst Case Condition.
What is the recommendation from Cypress to ensure that the Individual Power Switching Modes is always detected with 100k pull down resistor, even under worst case condition.
Thanks & Regards
The actual measured maximum leakage current is much lower than the 10 uA mentioned in the datasheet as confirmed.
Q1. Yes your understanding is correct.
Q2. The condition of 10 uA leakage current shouldnt occur, it should be even lower than 8 uA which can be checked from our DVK so the drop created wont be seen as high even under worst case condition.