10 Replies Latest reply on Sep 10, 2018 5:52 AM by JacobLerenius

    What is the timing during Sequencing Successive Approximation

    JacobLerenius

      I'm trying to find what the timing is when using the Sequencing Successive Approximation component in 5LP. The important parts are:

      1. Time from mux-in to ADC start

      2. Length of ADC

      3. Time from ADC finish to mux-out.

      When looking at the input signal I can see the mux-in and the time it takes to stabilize, then some ringing during mux-out that seems to affect the result. I'm worried the last part of the SAR sampling is taking place during this ringing part as well. We see a 2-4 bit higher value than expected. The ADC inputs capacitance is rather high so a buffer with good driving capability is needed to acheive a stable value fast enough. I'm running the sequencer at 18MHz and testing with NCS20034 as buffer.

      Thanks for any input regarding this, Jacob

      NCS20034ToPSoC5LP_ADC_seq.png

        • 1. Re: What is the timing during Sequencing Successive Approximation
          vsrs

          Hello Jacob,

           

          Are you using a bypass capacitor ? Could you also tell the ADC settings ?

           

           

          Best Regards,
          VRS

          • 2. Re: What is the timing during Sequencing Successive Approximation
            JacobLerenius

            We are using an external reference and it is bypassed with 1uF on each pin.

            SAR_settings.png

            • 3. Re: What is the timing during Sequencing Successive Approximation
              JacobLerenius

              We tried using the really fast buffer (ADA4896), and even though the value has stabilized extremely fast (45ns), there is still an error if the previous value was on the other end of the ADC range by 7 ADC steps. If we change the SAR_CSR2_REG register to max delay (7) from the default (4) we get 0.9 AD steps error. When looking att the signal using an oscilloscope, the siglan looks perfect. Our conclusion is that there is some issue internally in the PSoC. Some internal BW limitation from the pin to the ADC? Do you have some verification data regarding the crosstalk when running the SAR sequencer at full speed?

              • 4. Re: What is the timing during Sequencing Successive Approximation
                brock_2468121

                I have had the same results you are seeing, errors from the previously sampled value. I have given up on the Sequencing SAR ADC. The convenience is not worth the inaccuracy. I have switched to an analog mux input, which is probably the same part that  the sequencing SAR uses, but I do two samples at each step and throw away the first. This is not the first device I've had to do this with. I've found with other manufacturers devices there is usually a small internal cap on the ADC input and the choices to get decent measurements are either charge the cap with a throw away sample cycle or over sample like crazy.

                • 5. Re: What is the timing during Sequencing Successive Approximation
                  user_411084576

                  Hi,

                   

                  Can you make sure that the clock to the ADC block is 18MHz. Internally generated clock frequency is lesser as the divider value is not possible. Please use a clock value which is multiple of 18MHz as the clock source.

                  • 6. Re: What is the timing during Sequencing Successive Approximation
                    vsrs

                    Hello Jacob,

                     

                    The ADC timing can be higher in case of hardware trigger. The total conversion time will around  4 cycles[sampling time - can be varied] + 14 cycles + 4 cycles [ Hardware triggering]. The 1Msps value is characterized, we have not characterized any problem at high frequency. You can try adjusting your clock to the right frequency and see whether there is improvement.

                     

                    Best Regards,
                    VRS

                    • 7. Re: What is the timing during Sequencing Successive Approximation
                      JacobLerenius

                      We tried changing the clock to exactly 18MHz. We had to go down to 32MHz (Max freq is 66.6MHz on the part and 54MHz fails to compile ("The internal clock minimum pulse width must be greater or equal to 25.5ns" error) and 32MHz was too low for our application. How would that make a difference to the issue we see? The problem now is that even though we run a buffer that is much faster than the time between mux-in and sampel on the ADC, we still get some error depending on the previous channel. And even though the value has setteled long before the sampling, it gets better when changing the delay from 4 (default) to 7. We have no idea why that is.

                      • 8. Re: What is the timing during Sequencing Successive Approximation
                        JacobLerenius

                        Thanks for your input. Not sure what timing can be higher in case of HW trigger. We use HW trigger now (PWM signal to the ADC sequencer).

                        You mention "the right frequency", how do you calculate that? You can see my answer to user_411084576 regarding the ADC frequency.

                        In your characterization, do you use several channels in the SAR Sequencer or are you just refering to the SAR? Our issue is when running multiple channels in the Sequencer, not between different measurements on the SAR. Do you have some information on how the channel looks (oscilloscope) when running at full speed with the precious channel on max and the observed channel at 0 or vise versa when you have no crosstalk issues? We'd like to see what the timing is in that case.

                        Thanks, JAcob

                        • 9. Re: What is the timing during Sequencing Successive Approximation
                          vsrs

                          Hello Jacob,

                           

                          Having the right clock frequency will help you to achieve the data-rate you need. Even though if you expect a higher data rate by giving clock, you will not be able to achieve it without a 18MHz(ADC clock needs to be that, you can use PLL or some other resources for this purpose so that your IMO frequency is not affected ).

                           

                          Now your problem seems to be due to a different reason. When you say that the signal is proper on scope, I hope you are probing at the pin input side. But the as you know there are routing resistances and sampling capacitor to the input of the ADC. The input you give into the ADC should be stabilized at the sampling capacitor for the output to be proper. When you are increasing the sampling time, you are giving enough time for the input get settled, but as you are unable to probe the input at the sampling capacitor point this is not visible.

                           

                          I hope that clears your doubt.

                           

                          Best Regards,
                          VRS

                          • 10. Re: What is the timing during Sequencing Successive Approximation
                            JacobLerenius

                            Thanks for the input.

                            Yes, the measurement shown earlier in this thread is at the input pin of the SoC. I can of course not measure internally on the ADC. But it shows clearly when the ADC capacitor is connected to the input pin by the internal mux, and the stabilization the signal. If I add a capacitor on the input and set the previous channel to a known value, I can see how the voltage on the input pin evens out really fast when the mux is set to the channel. So my conclusion is that the measurement I get on the external pin is close to what I would expect to se internally. But there must be something more going on internally that adds more error to the measurement. My guess is that there is a second layer of capacitance in the sample and hold part of the SAR, or similar,  that gives me this error and I don't see how I can improve the external signal performance even further to avoid this. If the internal capacitance is charged within limit, the rest is an intenal "back box". As I wrote earlier, we have a stable value after about 45ns! So we  a stable within 5% of the 1us sampling period. It is not realistic with a signal requirement for the SAR sequencer to work that is faster than this, right?

                            BR, Jacob