2 Replies Latest reply on Aug 31, 2018 3:55 AM by abga

    bring up the FX3 with the FPGA powered down and not worry about back feeding power

    user_305924230

      we had a bank of buffers between the FX3 and the FPGA added since our Alpha design with the following notation.

       

      BUFFERS U48, U51, U52, U53, U54, U56, U57

      We not in the Alpha design � see schematic attached.

      According to Greg’s notes

       

      1. Data flow is FPGA è FX3 for video and microphone (headset) transfers
      2. Data flow is FX3 è FPGA for headset audio output and in-system reconfiguration of the FPGA

      BUFFERS U48, U51, U52, U53, U54, U56, U57 (SN74AVC8T245RHLR) are level shifters that should provide isolation between the FX3_+2.5V and +2.5V domains such that when only VBUS is present, +2.5V will not be present. When +5V(DC jack) is only present, FX3_+2.5V should be ~0V.

       

      We believe there is a way to eliminate the buffers if we can configure the design correctly – see below.

       

       

      To Cypress customer service

      We are currently powering up the FX3 with an FPGA that is connected to the GPIF ports (DQ and CTL) however the FPGA is powered up separately to the same Voltage level.  We would like to be able to bring up the FX3 with the FPGA powered down and not worry about back feeding power from the FX3 IO to the FPGA..  One suggestion is just use the FPGA power to supply VIO1, 2 & 3.  If we implemented it this way, would PMODE and RESET_N  still work?  That would be a hardware fix that may or may not affect the reset function.  Another possibility is more of a software fix and that would be to tristate the CTL and DQ ports as it powers up and leaving them tristated until we know the FPGA power is good.  Please refer to page 5 of our schematic.

      Thanks

      Tom Minnis