8 Replies Latest reply on Aug 13, 2018 5:52 AM by user_342122993

    Current mode switching regulator in psoc

    user_266323844

      I want to use a psoc5 or psoc5lp to build a programmable current mode pwm controller for a switching regulator. I have a freesoc  and a freesoc  mini that I can use for prototyping, so my preference is psoc creator 2.2, sp1, but if that is too limiting, then I can switch to a cyc8kit, and a later version of psoc creator.

       

      This is a standard buck regulator configuration. The primary switching element is a MOSFET. There is a current sense resistor after the inductor to measure inductor current. The current sense voltage is amplified by an external opamp (due to the large voltages involved).

       

      current-mode-pwm.png

       

      Please note that resistor, inductor, and capacitor values have not been calculated yet; those components are placeholders.

       

      This will be a standard double-loop current mode supply:

      1. Each cycle is initiated by a free-running clock.
      2. The clock sets a RS flipflop. (NOTE: the schematic above needs an edge-detector)
      3. When the flipflop is set, the gate of Q3 is driven high, which turns on Q2 and starts current flowing through L1
      4. U3 measures the current through L1 using sense resistor R1 and feeds that back into the PSoC to Comp_1.
      5. When Comp1 goes low, it resets the RS flipflop, turning off Q3 and Q2.
      6. The positive input to Comp_1 comes from a VDAC
      7. To close the outer feedback loop, the output voltage is measured by R10 and R11 and fed into a SAR ADC.

       

      Here is the part I haven't implmented. I want to take the output from the SAR ADC, subtract it from a setpoint, then load that into a down-counter in order to implement slope compensation. The output of the down-counter should be the input to the VDAC.

      1. The setpoint comes from a data register
      2. The setpoint is compared with a measured value to obtain the error value (subtractor)
      3. The error value is decremented gradually to implement slope compensation (down counter)
      4. The error value is sent to a VDAC

       

      I have not been able to work out how to:

      1. Get the raw output from the SAR ADC
      2. Create a CPU-accessible data register
      3. Subtract the raw output from the data register
      4. Load the result into a counter
      5. Supply the counter output to the VDAC

       

      Now, I know that I can implement these functions in Verilog very easily, but I don't think that the compiler will produce code that uses the UDBs. How can I build this in PSoC Creator? I'm certain that this is all doable with UDBs and it must be very similar to implementing an all-hardware PID loop. I want to fit 4 of these controllers into one PSoC so getting it to work with UDBs is important.

       

      Is it doable with PSoC creator 2.2 SP1? Or do I need to switch to a later version for more control over UDBs and buy a new PSoC 5LP development platform?

        • 1. Re: Current mode switching regulator in psoc
          user_342122993

          Out of tasks #1-5, only #3 (subtract) and #4 (count down) require hardware resources. Implemented in Verilog,  8-bit configuration will consume about 5% of macrocells only, so there should be no problem to do it in Verilog entirely.

           

          To get acces to the ADC_SAR raw data use modified ADC component with digital output bus

          Re: ADC Direct Digital Output - Route to UDB/Logic

          ADC_SAR_LPF_2x_01.png

          The above project also has LPFilter component, which "may" serve as a substitute for a counter (at least for some testing).

           

          The example of instantiating CPU-accessible ControlReg in Verilog can be found here:

          http://www.cypress.com/comment/392376#comment-392376

           

          FreeSoc and FreeMini are excellent boards and work with latest Creator (v4.2). The v4.2 can read files from older versions, but v4.0 and below can not read 4.2. I use mostly 4.0 for that reason. You may consider also KIT-059, which is comparable with FreeMini (once it blows up).

          http://www.cypress.com/documentation/development-kitsboards/cy8ckit-059-psoc-5lp-prototyping-kit-onboard-programmer-and

           

          Please share your results with the community.

           

          /odissey1

          • 2. Re: Current mode switching regulator in psoc
            user_463759797

            In regards to the version of PSOC creator to use, and the version of PSOC5 to use, I have some comments.

             

            First, PSOC5 has been End-Of-Life'd.  PSOC5LP is current production.  Use the PSOC5LP.

             

            Second, the freesoc boards are good, but Cypress also has a $10-$15 dollar board available from Cypress or from places like Mouser (mouser.com)  You could spend the $10 and dedicate it to that project.

             

            Third, I would recommend PSOC Creator 3.3, especially if you are using VMWare to host.  The reasons are, that starting with PSOC Creator 4.x, there is 1) absolutely no backwards compatibility of projects, and 2) if you use the kitprog compatible debugger on either freesoc or their $10 board, it can take up to 6 seconds per debug step when going through source code when using Version 4.x of PSOC Creator.

             

            The reason that the debugging is so *very* slow appears to be that the engineers tried to avoid stepping into interrupts for each source code line step.  The kitprog is a slow serial link, and that *really* drags the debug process out.  1 minute to step 10 lines of code.

             

            The 3.3 PSOC Creator is the last version that does not do this.  The bad part of using 3.3 is you have to disable interrupts after you reach your breakpoint.  Then you step into the last triggered ISR and out one again, but only one time, then you can keep single stepping through the rest of your code, 10 lines of code in under 10 seconds.

             

            For us here, we have standardized on PSOC creator 3.3 for PSOC5LP for that very reason.  We might go to 4.x if we use future processors, but our engineering costs are such that stepping through 150 lines of code should not take one-quarter of an hour!

            • 3. Re: Current mode switching regulator in psoc
              user_266323844

              Somehow, I forgot that the FreeSoC was upgraded to PSoc5LP half-way through the Kickstarter. Looks like I can use the more recent Creator versions after all.

               

              WIth that ADC and the more recent creator version, I am now making some progress. I'll update some more later.

              • 4. Re: Current mode switching regulator in psoc
                user_342122993

                I would add that prior to diving in to hardware control, try to do it in code. CPU can easily handle it at about 100k interrupts/sec, which is enough for this. Later on it can be shifted to UDB to free CPU for other tasks.

                /odissey1

                • 5. Re: Current mode switching regulator in psoc
                  user_266323844

                  Now, I'm having difficulty working out how to map the data from the UDB component to my DAC. Is this a job for DMA?

                  • 6. Re: Current mode switching regulator in psoc
                    user_266323844

                    I'm hoping to run this PWM at 1MHz at the minimum, so part of it absolutely must be run in hardware, but that's the easy part: setting the current limit (DAC) and comparing the received current sense signal (comparator). I don't really know if it is necessary to implement the datapath in hardware. Given that the VDAC has a maximum sample rate of 1MHz, I don't think I can implement 1MHz slope compensation digitally, which means that it's just the voltage feedback path. Since I have very slow load transients, it's likely acceptable to set that in software as you say.

                     

                    Implementing slope compensation looks like it would take analog blocks: an integrator and a subtractor. I haven't seen these components from Cypress, but maybe there are user-contributed ones.

                    • 7. Re: Current mode switching regulator in psoc
                      user_342122993

                      The VDAC8 has bus input and strobe. As an example, the DAC input bus can be attached to the LPFilter output in the above demo project (ADC-LPF).

                      DMA works well also between LPFilter and VDAC, I can make a demo if you need one.

                      /odissey1

                      • 8. Re: Current mode switching regulator in psoc
                        user_342122993

                        Working at 1 MHz is challenging. That is analog 'frontier' for PSoC (ADC, DAC, OPAMP). Then there is a prototyping board (FreeSoC) with long wires and large on-board cross-talk. I would start with 200 kHz switching frequency, and slowly increment it with project advance.

                        I am not familiar with power control circuits, but can review your project, if there are some issues.

                        /odissey1