I need some help or reassurance in the following:
I have implemented a design whose purpose would be to act as a 'man-in-the-middle' in a non-standard paralel bus communication.
I've created a component with Verilog implementation in which the byte-wide databus is bidirectional, therefore I also instantiated 8 BUFOE modules which are connected to the PSOC 5LP bidirectional digital pins. The Data bus is driven by the MASTER on the DATA pins, except when a read cycle is initiated in which case the SLAVE gains control over the DATA bus. The slave drives the DATAO pins.
After building the design with a newly created component, the following warning appeared:
"Warning-1366: Setup time violation found in a path from clock ( Clock_ibus ) to clock ( Clock_ibus )."
(note: my Master Clock is 48MHz)
After opening the STA report, the following was highlighted as the timing violation:
Upon closer inspection I found that the accumulated delay is made up of these steps:
I have attached the Verilog implementation of my component below, but here's a block diagram of the relevant hardware elements:
My assesment of the situation is that the Static Timing Analyser, built in the PSOC Creator, is ignorant about the OE and its inverted pair -OE signals and their effect on the BUFOE components.
In the analysis I can see how the signal originates from my MUX-ed registers, go through the BUFOE, take a U-turn in the iocell (the physical pin, so to speak), go around the BUFOE's fb (feedback) signal, straight into the other BUFOE, another U-turn at the other bi-directional pin, and straight back to my bufreg's input via the din (fb) wire. This whole route is supposed to be completed within a clock cycle + setup/hold times, no wonder the signal propagation delay is a blasted 79+ nanoseconds. In reality, when the OE signal is LOW (-OE is HIGH), the data on dout never reaches the DATA pin. When the OE signal is HIGH and -OE is LOW the data never reaches the DATAO pin.
Knowing how the BUS protocol and my hardware control these signals, I plan to ignore this warning, but use the STA report to calculate reasonable clock frequency (24MHz).
My question would be: Am I right? Can I ignore the STA warnings? If yes, is there any way to make the STA to calculate with the right parameters/constraints(or whatever)? I skimmed through the PSOC Creator User Guide's but found nothing helpful (Directives included...)
IBUS_Unit.v 12.9 K