CY8CKIT-062-BLE Setup Only requires PDL 3.0.1

[RoKe_2291266]

The CY8CKIT-062-BLE Setup Only software will not install if PDL 3.0.3 is installed and not 3.0.1, since it seems to want only PDL 3.0.1. It seems to me that it should check only for a minimum version and should allow newer versions. In fact, it seems that it should install even if PDL is not installed at all, since PDL is required only for building.

[jomoc_3144201]

I'm seeing something similar where if I use PDL 3.1.x the code compiled does not work on the CY8CKIT-062-BLE.  If I down rev the PDL to 3.0.1 the same compiled code works without issue on the CY8CKIT-062-BLE.

Is 3.0.1 required for the PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) and anything newer than 3.0.1 not supported with this board?

Cheers,

Jon

[MotooTanaka]

Hi,

Recently I encountered similar situation and I found following.

(1) Current schematic of CY8CKIT-062-BLE shows that the PSoC 6 on the board is CY8C6347BZI-BLD53

(2) My board, which is Rev 11, has CY8C6347BZI-BLD43

(3) My colleague's board, which is Rev 8, has CY8C6347BZI-BLD53ES

So my guess is that CY8C6347BZI-BLD43 (and may be CY8C6347BZI-BLD53ES) requires PDL 3.0.1.

Meantime the newer CY8CKIT-062-BLE (Rev 13~?) requires later version of PDL, such as PDL 3.1.x.

May be we need to specify the Rev of the board when we talk about CY8CKIT-062-BLE

otherwise we are talking about different boards and condition(s) may not be same for each Rev(s).

moto

[jomoc_3144201]

Good observation.

I have a board which is labeled Rev. 8 and PSoC Programmer reports that it detected a CY8C6347BZI-BLD53 which is the processor I use for it with PSoC Creator. I have been able to use PDL version 3.0.4 with this and PSoC Creator  but a warning does appear where some files needed to be updated in the project.  I just clean the project and run Generate Application and Build the project again before loading it on the board.  This seems to work nicely.  However, I have had no luck with PDL 3.1.  Thus far, I have not found the magic formula to get this to work with the BLE Pioneer kit I have.

My suspicion is that ModusToolbox is using a version of the PDL that is inline with PDL 3.1 which is why there is an issue with it working with the older BLE Pioneer kit. The other thing I have noticed is that ModusToolbox does not create a .hex file but rather a .elf file to load in the board thus this can not be installed using PSoC Programmer.

New tools, new challenges.

[jomoc_3144201]

The latest firmware revision doc for the  CY8CKIT-062-BLE  shows CY8C6347BZI-BLD53.

http://www.cypress.com/file/385706/download

Was the board recently updated to CY8C6347BZI-BLD43  recently?  The two chips seem to have different features though.

[MotooTanaka]

This is my board Rev 11

The silk print states CY8C6347BZI-BLD43.

So I suppose it has been -BLD43 since I purchased the board.

And as you mentioned, there are difference(s) between BLD53 and BLD43.

BLD53 has CTBM x 1 and UDB x 12,

BLD43 has CTBM x 0 and UDB x 0,

and I would imagine that there are more difference(s) between these, two.

Meantime I have no information about BLD53ES which was mounted on my colleague's Rev 8 board.

(I wonder which chip is mounted on your Rev 8 board)

Anyway, just FYI.

moto

[jomoc_3144201]

Odd, the silk screening on your Board shows BLD43 but the marking on the chip looks like it shows BLD53ES.  My board only shows PSoC 6 BLE under the chip but the marking on the chip does show BLD53ES so I'm thinking the ES is just an extra designation since it does not show from PSoC Programmer. 

What does PSoC Programmer show for your board with the BLD43 marking?

[MotooTanaka]

Wow, I've been believing that the chip on my board was BLD43, since the silk states so.

But yes as you mentioned, if I enlarge the picture enough I can read it as BLD53ES, too.

In our industry, ES usually stands for "Engineering Sample",

which is a very early version of the device.

So I may be able to re-state what I was thinking  to ...

PDL 3.0.x works with the BLD53ES but PDL 3.1.x is required for BLD53.

Since I'm out of the office and it's a 3 day's weekend in Japan,

it will be Tuesday when I can test my board with PSoC Creator.

moto

[jomoc_3144201]

If 'ES' does indicate Engineering Sample, then why would Cypress sell boards with this chip installed?  That is strange.

However, with the board I have, both PSoC creator and PSoC Programmer show that this is a BLD53 and does not show the 'ES' notation when listing the device.  In either case, I am able to use PDL 3.0.4 but not PDL 3.1.

[MotooTanaka]

> If 'ES' does indicate Engineering Sample, then why would Cypress sell boards with this chip installed?

Since I'm not working for Cypress nor I represent Cypress I have no idea either.

> In either case, I am able to use PDL 3.0.4 but not PDL 3.1.

Yes, probably this is the bottom line, it seems that

BLD53ES requires PDL 3.0.x

BLD53 requires PDS 3.1.x

moto

[MotooTanaka]

FYI

With PSoC Creator

CM0p

CM4

With PSoC Programmer

So these tools reported that the device on my board, which is Rev 11, is also CY8C6347-BLD53.

And according to PSoC Creator both CM0p and CM4 are "PRODUCTION"

moto

[MeenakshiR_71]

Hello Moto/Jon,

Just to clarify "ES" does mean "Engineering Sample" and the kits that you have does have ES marked parts.

Every PSoC silicon (PSoC 3/4/5/6) and for that matter any silicon, run through various stages of production. The ES stage of PSoC/Cypress silicon that is shipped out to customers, is when we have validated all the functionalities of the silicon and completed char (datasheet electrical specification) of key specs. However, at the ES stage, some of the datasheet specs are still not characterized and the optimization of yield (manufacturing process optimization) are not in place i.e. we will be getting lesser number of silicon per wafer during the ES stage. The next stage for the samples we ship to customer is Production and at this point, it is usually char'ed fully (datasheet will no longer have preliminary tag) and the yield is optimized to produce maximum amount of silicon possible per wafer.

Now what the above mean to customers that have ES sample silicon - nothing At the production stage, it is the same existing ES silicon that is qualified for production. Only when some char/specs go out of spec from the preliminary datasheet, depending on the impact of the spec, we either update the spec, put an errata in final datasheet or if it is really major and non-acceptable go for another version of the silicon (very very rare case). In the latter case, existing ES sample customers will be usually informed of the impact/issue.

Now why would we ship ES sample silicon to customers (kits) - just to give customers as early access to our products as possible and at the ES stage that we release to customers, we have confidence in the silicon (functionality and key specs in check ). In addition, the ES samples are not shipped in bulk quantities as only at the Production stage, we will be ready for bulk shipping (mfg process optimization I mentioned above).

Hope this clears some air Let us know if you have any clarifications or concerns around this.

Regards,

Meenakshi Sundaram R

[MeenakshiR_71]

Jon,

Can you post a pic of the Silicon in your board? I would like to check the silicon rev (like Moto's post).

It appears like PDL 3.1.0 removes support for Rev *A version of the silicon (and hence may not work if your kit has that silicon rev).

Regards,

Meenakshi Sundaram R

[MotooTanaka]

FYI, attached is my colleague's Rev 08 board.

The silk reads

============

CY8C634

7BZI-BL

D53ES

1725 62

7207

===========

moto

[MeenakshiR_71]

Thanks Moto, this is a Rev *A board (date code 1725 ==> WW25, 2017). The image that you posted earlier had Rev *B (1743 or higher).

============

CY8C634

7BZI-BL

D53ES

1725 62

7207

===========

So yeah if your board has date code of <1743, then the board is Rev *A. Alternately, you can read the "SFLASH->SI_REVISION_ID" or "Cy_SysLib_GetDeviceRevision" in firmware to check if it is Rev *A (0x21) or not.

I am trying get confirmation on whether the support for *A has been removed from 3.1.0 or not. I will update the post once I have a confirmed answer.

Regards,

Meenakshi Sundaram R

[jomoc_3144201]

I can confirm the board I have does have a "1725 62 7207" date code on it.  If it is true regarding the removal of the Rev A chip from PDL 3.1, then this explains why a board with this revision chip on it does not work with ModusToolbox.

Thanks,

Jon

[MeenakshiR_71]

Jon/Moto,

I just got hold of a *A board and confirmed that it does break for *A silicon and works for *B and *C.

I did some additional debug on the issue and figured that a difference in "startup_psoc6_01_cm0plus.S" is messing things up. The old startup file had definition for "Cy_SaveIRQ" and "Cy_RestoreIRQ" APIs, which is removed in the new file. I suspect that these definitions were used by *A si flash boot and from *B onwards these definitions might have been moved as part of the boot code itself. Thus resulting in hung code in boot.

Can you try the attached startup file (M0+) in Modus or PSoC Creator with PDL 3.1.0 and see if that works? It did the trick in my setup at least.

I have raised an internal defect ticket to get this checked.

Regards,

Meenakshi Sundaram R

[jomoc_3144201]

Meenakshi,

I have confirmed your change does work with the CY8CKIT-062-BLE version I have and PSoC Creator 4.2 and PDL 3.1.0.   I have not tried this with ModusToolbox as of yet.

Nice work.

Jon

[MotooTanaka]

Dear Meenakshi-san,

Thank you very much for the Startup!

I backed up and replaced startup_psoc6_01_cm0plus.S at

C:\Users\<MyUserName>\ModusToolbox_1.0\libraries\psoc6sw-1.0\components\psoc6pdl\devices\psoc6\startup\gcc

I tried new BlinkyLED Project for CY8CKIT-062-BLE (Rev 11).

And for the first time I could debug and run the program from ModusToolbox with my CY8CKIT-062-BLE!

Best Regards,

27-Dec-2018

Motoo Tanaka

P.S. I have confirmed that this also worked with my Colleague's CY8CKIT-062-BLE (Rev 😎

[CoreyW_81]

I know that this is an old thread, but a question came up regarding using PDL 3.0.4 for all future PSOC 6 iterations.  I am concerned that if I have some of my boards in the field with ES silicon, and then a number of boards with *A, *B ... and newer, that somehow Cypress will prevent the use of 3.0.4 on the newer revisions of silicon.

Is there anything preventing me from continuing to use 3.0.4 so that any updates that need to go out to my customer will ALWAYS work?

[MotooTanaka]

Hi,

It's been a while I was discussing in this thread,

and in this thread with ModusToolbox 1.0 with PDL 3.0.1

we could use ES version of devices with a little bit of hack.

Then when ModusToolbox 1.1 came up,

I was somewhat upset that it discards the support of ES version devices.

Please refer to the thread below.

Wow to ModusToolbox 1.1!

For better or  worse, it's the real life,

although for me it was a matter of single board,

your case seems to be more serious.

I am very sorry for hearing your problem.

IMHO, I hope that you can keep on the working version of environment for the existing systems.

moto