6 Replies Latest reply on Aug 21, 2018 10:37 PM by nsha

    How to improve parasitic capacitance for CY8CMBR3116

    ohairscott_3600456

      I am using the CY8CMBR3116 in a design. The farthest three buttons are being automatically turned off due to high parasitic capacitance. Their values are as follows:

       

      CS1     DEBUG_CP: 46

      CS11     DEBUG_CP: 46

      CS12     DEBUG_CP: 49

       

      I do not believe this number should be so high. My design is four layers, round sensor shapes with 16mm diameter, top layer is a 45mil hatched shield, layer two is 70mil hatched ground and sensor traces, layer 3 is 70mil hatched ground, bottom layer is 70mil hatched ground and CapSense controller. No other traces run over my sensor traces, and the clearance around the sensor traces to hatched ground is 7 mil. Traces are 7mil. Trace lengths are: 114mm for CS12, 91mm for CS11 and 113mm for CS1.

       

      My current plan to lower parasitic capacitance is:

           -increase the clearance around the sensor traces from 7mil to 20mil

           -possibly remove layer 2 and layer 3 hatched grounds

       

      I want to lower the parasitic capacitance so that I am able to use auto-tuning (pF <= 45). Is anything standing out that I can change in hardware or software that will help lower the parasitic capacitance? Thanks!

        • 1. Re: How to improve parasitic capacitance for CY8CMBR3116
          nsha

          Hello,

           

          Yes, the recommended button-ground clearance should be a minimum of 0.5 mm (20 mil).

          You can also connect the layer 2 hatch to shield instead of ground. This would reduce Cp.

           

          Also, is it necessary to have 16 mm diameter buttons? What is the overlay material and thickness used?

          You can refer to MBR 3xxx CapSense design (Design toolbox) to decide on the sensor dimensions.

           

          Unfortunately, there is no change that can be done in software.

           

          Thanks,Shanmathi

          • 2. Re: How to improve parasitic capacitance for CY8CMBR3116
            ohairscott_3600456

            The 20mil button ground clearance lapse was me forgetting to add the rule to the net (whoops). I will definitely add this in my next revision. I can drop the size of the buttons down, this will not be an issue. Is there an optimal size I should go for?

             

            I also will change layer two to be hatched shield. Is it okay to leave layer 3 as hatched ground? I can change this to active shield if it will help.

             

            The material will be ~5mil ABS plastic. I have not been testing with the material on the sensors yet, should I expect the Cp to increase significantly after attaching the material?

            • 3. Re: How to improve parasitic capacitance for CY8CMBR3116
              nsha

              Hi,

               

              You can better use a three-way switch, so that you have provision to change the hatch to shield/ground.

              If you use ground, there is better noise immunity. Whereas, if you shield, Cp of sensors is less.

               

              So, after redesigning your layout, depending on the Cp and performance of sensors. you can connect the hatch.

               

              Since the overlay you are using is very thin (5 mil), you can reduce the button dimension to 8-10 mm.

              Using the design toolbox (mentioned in previous post), I see that the minimum recommended button diameter is 5 mm. Hence, 8-10 mm diameter should work great for your design.

               

              I suspect the sensors to be highly sensitive as you are using a thin overlay thickness. If you face a high sensitivity issue, then increase the overlay thickness to 0.5 mm.

               

              Best regards,
              Shanmathi

              1 of 1 people found this helpful
              • 4. Re: How to improve parasitic capacitance for CY8CMBR3116
                ohairscott_3600456

                Adding a switch is a great idea, I'll make your recommended design changes and hopefully will be able to drop the Cp. Thank you for your help!

                • 5. Re: How to improve parasitic capacitance for CY8CMBR3116
                  ohairscott_3600456

                  I was able to make the changes recommended by nsha from above. I'll post the results of my tests for anyone who is curious.

                   

                  The changes that I made:

                       -Increased clearance area around CapSense traces from 7mil to 25mil

                       -Reduced sensor size from 16mm diameter to 12mm diameter

                       -Added two jumpers that allowed me to independently switch hatched layer 2 and hatched layer 3 to be active shield, ground or disconnected

                   

                  Results of the different jumper positions are below. CS1 trace is 122mm from CapSense, CS11 trace is 103mm and CS12 is 123mm.

                   

                  Original issue (layer 2 and 3 are connected to ground):

                       CS1     DEBUG_CP: 46

                       CS11     DEBUG_CP: 46

                       CS12     DEBUG_CP: 49

                   

                  Layer 2 and Layer 3 jumpers disconnected:

                       CS1     DEBUG_CP: 23

                       CS11     DEBUG_CP: 23

                       CS12     DEBUG_CP: 24

                   

                  Layer 2 active shield, Layer 3 active shield:

                       CS1     DEBUG_CP: 30

                       CS11     DEBUG_CP: 29

                       CS12     DEBUG_CP: 30

                   

                  Layer 2 ground, Layer 3 active shield:

                       CS1     DEBUG_CP: 33

                       CS11     DEBUG_CP: 32

                       CS12     DEBUG_CP: 33

                   

                  Layer 2 active shield, Layer 3 ground:

                       CS1     DEBUG_CP: 24

                       CS11     DEBUG_CP: 24

                       CS12     DEBUG_CP: 24

                   

                  Layer 2 ground, Layer 3 ground:

                       CS1     DEBUG_CP: 33

                       CS11     DEBUG_CP: 31

                       CS12     DEBUG_CP: 33

                   

                   

                  Interestingly enough the lowest parasitic capacitance values came from leaving both layer 2 and layer 3 hatched fills as disconnected. I did not expect this result. The close runner up is layer 2 active shield and layer 3 ground, with about a 50% reduction in Cp. I chalk most of the improvement up to the 25mil spacing, so make sure to leave plenty of room between traces and ground fills!!!

                   

                  I plan to use the layer 2 active shield and layer 3 ground in my final design.

                   

                  Thanks for the help nsha!

                  • 6. Re: How to improve parasitic capacitance for CY8CMBR3116
                    nsha

                    You are welcome Scott! Thank you for posting the results!

                     

                    Regards,
                    Shanmathi