4 Replies Latest reply on Aug 3, 2018 4:23 AM by eded_3346251

    Problem with SPI-Logging, 2 Slaves receive alternately

      Hello community,

      i want to use the PSoC for logging SPI-Data and need some help.

      First i simulate with another PSoC 5lp a simple Datatransfer from PSoC to SRAM "23LC1024". (Master_Transmission.zip)

      Next i designed on the 2nd PSoC-5LP a Datalogger with two SPI-Slave Blocks and one SPI-Master Block. (SPI-Logger.zip)

      The First PSoC transmit 100Bytes (0x1,0x2,0x3,0x4,0x5.....0x64   Diagram1&2) and the 2nd PSoC catch them and store them in another SRAM "23LC1024". (Diagram3) (The first 4 Byte are InstructionByte for the SRAM)


      Diagram 2
      Diagram2.PNGAfter a timeroverflow the PSoC-Datalogger load all Data from the Flash and send them to the computer, where the Data can be displayed with "Putty".(Diagram5)

      Its important that i get all transmitted data, thats the reason i use two Slaves alternately. So the 2nd Slave can receive the next data, while the 1st Slave is busy with storing them in the Flash. That was my last idea to hold the Timing without losing data. (Master Clock = 2Mhz / Logger-Clock = 16Mhz)


      Diagram 1



      Diagram 3




      The Problem is the 2nd Slave-Block respectively the receiving/Bufferswitch technique behind this. You can see in Diagram 3, that the first 20 Byte are correctly received and transmitted. But the next 20 Bytes and all other Bytes from the 2nd Slave are wrong.
      Should be: 0x11,0x12.....0x24

      Actually is: 0x32,0x41,0x51,0x61....0xe1,0x2,0x12,0x22,0x32,0x42,0x52,0x62 (Diagram 4 & 5)


      Diagram 4



      Diagram 5


      My question is, whats wrong and how can i catch the right transmitted data correctly with both Slaves in the right order.

        • 1. Re: Problem with SPI-Logging, 2 Slaves receive alternately

          Hi Edward,


          I am suspecting that that switching between two slaves is not fast enough compared to the stream of bits coming from the master. Can you bit bang a pin at the end of the "WakeupIsr" and see if the switching happens before the start of next set of bytes?


          Nevertheless, the timing is too critical in this design to be executed in firmware. Is there any reason why you can't use one SPI and load all the bytes, not just 20 and then write into flash/SRAM?



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          • 2. Re: Problem with SPI-Logging, 2 Slaves receive alternately

            Hi Rajiv,


            thank you for your advice, i already have one "Control"-Pin for each SPI-Slave/DMA output. These "Control"-Pins send a HIGH-Pulse and definetly switching in the right order. The Logic Analyser shows an evenly time-delay of 40µs from the HIGH-Pulse to the store-transmission in both cases.   
            Example: (Control-P1_~40µs_1st-Tranmission_~18µs_Control-P2_~40µs_2nd-Tranmission_~18µs_Control-P1_~40µs_...).



            The reason for this design is, that i don't know how many Bytes will be transmitted in reality.
            This transmission of 100 Bytes, is a simulation and i need to catch all possible Bytes.
            Its possible to increase the number of received/stored Bytes, and the number of transmitted bytes. This should increase the period of time,
            i will try it.
            But i think the problem should be something in the 2nd Array-storage.




            • 3. Re: Problem with SPI-Logging, 2 Slaves receive alternately

              Hi Edward,


              Can you send a screenshot with the Master data and the debug signal generated after switching the slave? This suspicion is coming because if the first slave is working correctly, i was expecting, the third row of data should have started from 0x25 instead of 0x29. Please correct me if I am wrong here. Just looking at the stream of data, it is looking like 2 1/2 bytes, that is,  20 bits of data missed during the switching. For example, in the second row data which is captured by the second slave, is reading 0x31, 0x41, 0x51....instead of 0x11, 0x12, 0x13, 0x14, 0x15. It looks like 0x11, 0x12, 0x1_ was not captured. I may be completely wrong. The waveform capture showing the alignment of debug signal (toggled after changing the slave in firmware) with respect to the master data will give clear picture.



              1 of 1 people found this helpful
              • 4. Re: Problem with SPI-Logging, 2 Slaves receive alternately

                Hi Rajiv,


                your guess was right, my switch technique with two Slaves was not fast enough. I tried to store 100 Bytes but nevertheless i got losses in the reception. The reason for the "brocken" Bytes in the secound transmission was an asynchronous time-offset.

                I have changed the logic to one Slave again and add some logic-gates to switch between the two storage-DMAs (look at Circuit Diagram). This techniqe was the solution for the Problem because the switching-Time is much faster ~2µs. (look at Timing Diagram)

                Now my PSoC catches all transmitted Bytes without losses.


                Nevertheless thank you for your advice.

                best regards



                Circuit Diagram:



                Timing Diagram: