10 Replies Latest reply on Jul 24, 2018 7:01 PM by yzhc_1339276

    FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

      Hello, everyone.

      I have related development experience with cyusb3014. In order to quickly integrate FX3 to our system, we used CYUSB3KIT-003. And it worked normally.


      About three weeks ago, the CYUSB3KIT-003 was broken. and I bought another board to replace it. but something strange happened.


      It couldn't work as expected. But we just used the same FPGA, same Verilog program, same connection with CYUSB3KIT, same fireware image file.


      In our system, the synchronous slave fifo mode is used. However, FPGA cannot receive the data from FX3. according to the sampling of the signal line by chipscope,

      the control signals are normal, that is, slcs is low, slwr is high, and sloe, slrd is low, flagc turns low. but there is no validate data on the data bus although  Control Center has sent data to FX3.


      and for the previous broken board, the system just run normally.


      why can this happen? how to figure this out? any ideas? Thank you very much.