If don't enable "EXT_VCCD" bit manually, how about the result? Please check if there are any external noises on XRES pin.
In addition, you could use CySysGetResetReason() to observe the reason of reset.
Thank for your reply.
- The results are the same w/wo enabling the ËXT_VCCD” bit.
- The device case (16 QFP) does not have XRES pin.
- The resets appear exactly every 0.8 seconds, so it can’t be noise! (more common to be some kind of Brownout or watchdog, but it’s not)
- We don’t know how to check the CySysGetResetReason as we get this rapid reset.
in debug mode everything is working fine but upon stopping the debug mode the resets appear at constant frequency.
It looks like some kind of watchdog although it is not enabled.
In debug mode, WDT interrupt won't work. That matches the issue phenomenon.
In clock tree GUI(double-click ILO under Clock tab in .cydwr), is WDT configured?
Below code can be used in main() to detect if WDT Reset occured.
/* Enable global interrupts. */
if(CySysGetResetReason(0) & CY_SYS_RESET_WDT)
It was a problem with the watchdog while getting interrupt.
It is okay now.
Thanks for your assistance.