Hello Liu Hengliang,
Please check the FIFOADDR Lines. It must be held constant during the PKTEND# assertion.
I just have one FX3 as slave FIFO , so i set the A[1:0] as constant value 0 in FPGA. It looks like no problem.
Any other suggestions ?
1. Please confirm whether your using the slave fifo example code provided with AN65974?
2.Please attach the slave fifo interface timing diagram.