Attached the modified project. I have selected specific pins and net constraint for successful routing. If you notice in the analog viewer in .cydwr, positive input of DelSig ADC connects to all the analog global left (AGL) lines, but negative input connects to only odd numbered lines. But in the design, you want pins to be able to connect to both input ends of the ADC (on consecutive AMUX channels). So, the pins that can connect to odd numbered AGL lines are selected.
Another way was to configure the AMUX and ADC in single ended mode and get the differential voltage in firmware.
You are a great help for me.
I was trying keep all pins contiguous.
Thank you so much.